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radeon/llvm: Add some comments and fix coding style

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This commit is contained in:
Tom Stellard 2012-05-07 14:52:11 -04:00
parent a8d82c44f7
commit f903da7335
8 changed files with 41 additions and 42 deletions
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37
src/gallium/drivers/radeon/AMDGPU.h
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@ -1,4 +1,4 @@
//===-- AMDGPU.h - TODO: Add brief description -------===//
//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
@ -6,10 +6,6 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
//
//===----------------------------------------------------------------------===//
#ifndef AMDGPU_H
#define AMDGPU_H
@ -19,25 +15,24 @@
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class FunctionPass;
class AMDGPUTargetMachine;
FunctionPass *createR600CodeEmitterPass(formatted_raw_ostream &OS);
FunctionPass *createR600LowerInstructionsPass(TargetMachine &tm);
class FunctionPass;
class AMDGPUTargetMachine;
FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
FunctionPass *createSIInitMachineFunctionInfoPass(TargetMachine &tm);
FunctionPass *createSILowerShaderInstructionsPass(TargetMachine &tm);
FunctionPass *createSIPropagateImmReadsPass(TargetMachine &tm);
FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
// R600 Passes
FunctionPass *createR600CodeEmitterPass(formatted_raw_ostream &OS);
FunctionPass *createR600LowerInstructionsPass(TargetMachine &tm);
FunctionPass *createAMDGPULowerInstructionsPass(TargetMachine &tm);
// SI Passes
FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
FunctionPass *createSILowerShaderInstructionsPass(TargetMachine &tm);
FunctionPass *createSIPropagateImmReadsPass(TargetMachine &tm);
FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
FunctionPass *createAMDGPUDelimitInstGroupsPass(TargetMachine &tm);
// Passes common to R600 and SI
FunctionPass *createAMDGPULowerInstructionsPass(TargetMachine &tm);
FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm);
FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm);
} // End namespace llvm
FunctionPass *createAMDGPUFixRegClassesPass(TargetMachine &tm);
} /* End namespace llvm */
#endif /* AMDGPU_H */
#endif // AMDGPU_H

2
src/gallium/drivers/radeon/AMDGPUConvertToISA.cpp
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@ -34,7 +34,7 @@ namespace {
virtual bool runOnMachineFunction(MachineFunction &MF);
};
} /* End anonymous namespace */
} // End anonymous namespace
char AMDGPUConvertToISAPass::ID = 0;

4
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
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@ -1,4 +1,4 @@
//===-- AMDGPUISelLowering.cpp - TODO: Add brief description -------===//
//===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
// This is the parent TargetLowering class for hardware code gen targets.
//
//===----------------------------------------------------------------------===//

5
src/gallium/drivers/radeon/AMDGPUISelLowering.h
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@ -1,4 +1,4 @@
//===-- AMDGPUISelLowering.h - TODO: Add brief description -------===//
//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,8 @@
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
// This file contains the interface defintiion of the TargetLowering class
// that is common to all AMD GPUs.
//
//===----------------------------------------------------------------------===//

21
src/gallium/drivers/radeon/AMDGPUInstrInfo.h
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@ -1,4 +1,4 @@
//===-- AMDGPUInstrInfo.h - TODO: Add brief description -------===//
//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,8 @@
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
// This file contains the definitoin of a TargetInstrInfo class that is common
// to all AMD GPUs.
//
//===----------------------------------------------------------------------===//
@ -21,17 +22,17 @@
namespace llvm {
class AMDGPUTargetMachine;
class MachineFunction;
class MachineInstr;
class MachineInstrBuilder;
class AMDGPUTargetMachine;
class MachineFunction;
class MachineInstr;
class MachineInstrBuilder;
class AMDGPUInstrInfo : public AMDILInstrInfo {
private:
class AMDGPUInstrInfo : public AMDILInstrInfo {
private:
AMDGPUTargetMachine & TM;
std::map<unsigned, unsigned> amdilToISA;
public:
public:
explicit AMDGPUInstrInfo(AMDGPUTargetMachine &tm);
virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
@ -42,7 +43,7 @@ namespace llvm {
DebugLoc DL) const;
#include "AMDGPUInstrEnums.h.include"
};
};
} // End llvm namespace

5
src/gallium/drivers/radeon/AMDGPULowerInstructions.cpp
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@ -1,4 +1,4 @@
//===-- AMDGPULowerInstructions.cpp - TODO: Add brief description -------===//
//===-- AMDGPULowerInstructions.cpp - AMDGPU lowering pass ----------------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,8 @@
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
// This pass lowers unsupported AMDIL MachineInstrs to LLVM pseudo
// MachineInstrs for hw codegen targets.
//
//===----------------------------------------------------------------------===//

4
src/gallium/drivers/radeon/AMDGPURegisterInfo.cpp
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@ -1,4 +1,4 @@
//===-- AMDGPURegisterInfo.cpp - TODO: Add brief description -------===//
//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
// Parent TargetRegisterInfo class common to all hw codegen targets.
//
//===----------------------------------------------------------------------===//

5
src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
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@ -1,4 +1,4 @@
//===-- AMDGPUTargetMachine.cpp - TODO: Add brief description -------===//
//===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,8 @@
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
// The AMDGPU target machine contains all of the hardware specific information
// needed to emit code for R600 and SI GPUs.
//
//===----------------------------------------------------------------------===//