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radeon/llvm: Remove AMDGPULowerShaderInstructions class

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It is no longer used.
This commit is contained in:
Tom Stellard 2012-05-08 10:04:44 -04:00
parent ad385c402e
commit 4226433625
6 changed files with 4 additions and 86 deletions
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1
src/gallium/drivers/radeon/AMDGPU.h
View file

@ -33,7 +33,6 @@ namespace llvm {
FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
FunctionPass *createAMDGPULowerInstructionsPass(TargetMachine &tm);
FunctionPass *createAMDGPULowerShaderInstructionsPass(TargetMachine &tm);
FunctionPass *createAMDGPUDelimitInstGroupsPass(TargetMachine &tm);

38
src/gallium/drivers/radeon/AMDGPULowerShaderInstructions.cpp
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@ -1,38 +0,0 @@
//===-- AMDGPULowerShaderInstructions.cpp - TODO: Add brief description -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
//
//===----------------------------------------------------------------------===//
#include "AMDGPULowerShaderInstructions.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
void AMDGPULowerShaderInstructionsPass::preloadRegister(MachineFunction * MF,
const TargetInstrInfo * TII, unsigned physReg, unsigned virtReg) const
{
if (!MRI->isLiveIn(physReg)) {
MRI->addLiveIn(physReg, virtReg);
MachineBasicBlock &EntryMBB = MF->front();
BuildMI(MF->front(), EntryMBB.begin(), DebugLoc(), TII->get(TargetOpcode::COPY),
virtReg)
.addReg(physReg);
} else {
/* We can't mark the same register as preloaded twice, but we still must
* associate virtReg with the correct preloaded register. */
unsigned newReg = MRI->getLiveInVirtReg(physReg);
MRI->replaceRegWith(virtReg, newReg);
}
}

40
src/gallium/drivers/radeon/AMDGPULowerShaderInstructions.h
View file

@ -1,40 +0,0 @@
//===-- AMDGPULowerShaderInstructions.h - TODO: Add brief description -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
//
//===----------------------------------------------------------------------===//
#ifndef AMDGPU_LOWER_SHADER_INSTRUCTIONS
#define AMDGPU_LOWER_SHADER_INSTRUCTIONS
namespace llvm {
class MachineFunction;
class MachineRegisterInfo;
class TargetInstrInfo;
class AMDGPULowerShaderInstructionsPass {
protected:
MachineRegisterInfo * MRI;
/**
* @param physReg The physical register that will be preloaded.
* @param virtReg The virtual register that currently holds the
* preloaded value.
*/
void preloadRegister(MachineFunction * MF, const TargetInstrInfo * TII,
unsigned physReg, unsigned virtReg) const;
};
} // end namespace llvm
#endif // AMDGPU_LOWER_SHADER_INSTRUCTIONS

1
src/gallium/drivers/radeon/Makefile.sources
View file

@ -42,7 +42,6 @@ CPP_SOURCES := \
AMDGPUISelLowering.cpp \
AMDGPUConvertToISA.cpp \
AMDGPULowerInstructions.cpp \
AMDGPULowerShaderInstructions.cpp \
AMDGPUInstrInfo.cpp \
AMDGPURegisterInfo.cpp \
AMDGPUUtil.cpp \

5
src/gallium/drivers/radeon/R600LowerShaderInstructions.cpp
View file

@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "AMDGPULowerShaderInstructions.h"
#include "AMDGPUUtil.h"
#include "AMDIL.h"
#include "AMDILInstrInfo.h"
@ -23,12 +22,12 @@
using namespace llvm;
namespace {
class R600LowerShaderInstructionsPass : public MachineFunctionPass,
public AMDGPULowerShaderInstructionsPass {
class R600LowerShaderInstructionsPass : public MachineFunctionPass {
private:
static char ID;
TargetMachine &TM;
MachineRegisterInfo * MRI;
void lowerEXPORT_REG_FAKE(MachineInstr &MI, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I);

5
src/gallium/drivers/radeon/SILowerShaderInstructions.cpp
View file

@ -13,7 +13,6 @@
#include "AMDGPU.h"
#include "AMDGPULowerShaderInstructions.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@ -21,12 +20,12 @@
using namespace llvm;
namespace {
class SILowerShaderInstructionsPass : public MachineFunctionPass,
public AMDGPULowerShaderInstructionsPass {
class SILowerShaderInstructionsPass : public MachineFunctionPass {
private:
static char ID;
TargetMachine &TM;
MachineRegisterInfo * MRI;
public:
SILowerShaderInstructionsPass(TargetMachine &tm) :