Commit graph

26978 commits

Author SHA1 Message Date
Samuel Pitoiset
1eca4c51a2 nvc0: bind images on compute shaders for Kepler
Old surfaces validation code will be removed once images are completely
done for Fermi/Kepler, that explains why I only disable it for now.

This also introduces nvc0_get_surface_dims() which computes correct
dimensions regarding the given target.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-04-26 19:47:49 +02:00
Samuel Pitoiset
c6b3c346d1 nvc0: reserve an area for surfaces info in the driver constbuf
To process surfaces coordinates from the codegen part, and because
some information like the format is not always available (eg. when
writeonly is used), we have to stick some surfaces data in the
driver constbuf. This is especially true for OpenCL because we don't
know the format at shader compile time.

This bumps the size of each shader area from 1K to 2K.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-04-26 19:47:49 +02:00
Samuel Pitoiset
afa04785fa nvc0: add preliminary support for images
This implements set_shader_images() and resource invalidation for
images. As OpenGL requires at least 8 images, we are going to expose
this minimum value even if this might be raised for Kepler, but this
limit is mainly for Fermi because the hardware only accepts 8 images.

Based on original patch by Ilia Mirkin.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-04-26 19:47:49 +02:00
Samuel Pitoiset
c62b1b92f7 gk110/ir: add emission for (a OP b) OP c
This is pretty similar to NVC0 except that offsets have changed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-04-26 19:47:49 +02:00
Samuel Pitoiset
3da8528846 nvc0/ir: fix wrong emission of (a OP b) OP c
The third source must be emitted at offset 49 instead of 17 and the
not modifier is at 52 instead of 20. If you look a bit above in
emitLogicOp() you will see that the dest is emitted at 17 which
confirms that src(2) is obviously wrong.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-04-26 19:47:49 +02:00
Jose Fonseca
dcc3baf733 gallium: Include intrin.h instead of defining ourselves.
More portable, particularly when building with Clang, which implements
all MSVC intrisincs in its own intrin.h, but doesn't actually support
`#pragma instrinsic`.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-26 17:17:00 +01:00
Jose Fonseca
9a25c8af1b scons: Whenever possible decide what to do based on platform and not compiler.
Because compilers like GCC and Clang are effectively available everywhere
so their presence/absence is seldom conclusive.

Furthermore, all compilers we use now have stdint.h.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-26 17:17:00 +01:00
Bas Nieuwenhuizen
31631d8515 radeonsi: Fix memory leak in error path.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-26 15:41:19 +02:00
Oded Gabbay
514c5b5f4b radeonsi: fix build error because of missing param
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-04-26 13:48:43 +03:00
Oded Gabbay
965175aba3 r600g: use do_endian_swap in texture swapping function
For some texture formats we need to take "do_endian_swap" into account
when configuring their swizzling.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-26 11:00:16 +03:00
Oded Gabbay
c86c761343 r600g: use do_endian_swap in color swapping functions
For some formats we need to take "do_endian_swap" into account when
configuring swapping for color buffers.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-26 11:00:16 +03:00
Oded Gabbay
686ad477bd r600g: set endianess of 16/32-bit buffers according to do_endian_swap
This patch modifies r600_colorformat_endian_swap(), so for 16-bit and for
32-bit buffers, the endianess configuration will be determined not only
by the color/texture format, but also by the do_endian_swap parameter.

The only exception is for array formats, which are always set to not do
swapping, because for them gallium sets an alias based on the machine's
endianess.

v4:
V_0280A0_COLOR_16_16 and V_0280A0_COLOR_16_16_FLOAT should be set to
8IN16 because the bytes inside need to be swapped even for array formats.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-26 11:00:16 +03:00
Oded Gabbay
2242dbe11d r600g/radeonsi: send endian info to format translation functions
Because r600 GPUs can't do swap in their DB unit, we need to disable
endianess swapping for textures that are handled by DB.

There are four format translation functions in r600g driver:

- r600_translate_texformat
- r600_colorformat_endian_swap
- r600_translate_colorformat
- r600_translate_colorswap

This patch adds a new parameters to those functions, called
"do_endian_swap". When running in a big-endian machine, the calling
functions will check whether the texture/color is handled by DB -
"rtex->is_depth && !rtex->is_flushing_texture" - and if so, they will
send FALSE through this parameter. Otherwise, they will send TRUE.

The translation functions, in specific cases, will look at this parameter
and configure the swapping accordingly.

v4:
evergreen_init_color_surface_rat() is only used by compute and don't
handle DB surfaces, so just sent hard-coded FALSE to translation
functions when called by it.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-26 11:00:16 +03:00
Dave Airlie
e3e6859381 tgsi: pass a shader type to the machine create and clean up.
There was definitely bugs here mixing up the PIPE_ and TGSI_ defines,
hopefully they didn't cause any problems, since mostly it was special
cases for GEOMETRY.

This clarifies at shader machine create what type of shader this
machine will execute. This is needed also for compute shaders where
we don't want to allocate inputs/outputs.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-04-26 13:05:32 +10:00
Dave Airlie
a6aae0c24d gallium/tgsi: move tgsi_exec.h header out of draw_context.h
It gets annoying that changing the tgsi exec rebuilds the state
tracker unnecessarily. Putting this include into draw_gs.h which
uses it causes a lot less rebuilds.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-04-26 13:00:57 +10:00
Roland Scheidegger
bd07e20d20 gallivm: make sampling more robust against bogus coordinates
Some cases (especially these using fract for coord wrapping) did not handle
NaNs (or Infs) correctly - the following code assumed the fract result
could not be outside [0,1], but if the input is a NaN (or +-Inf) the fract
result was NaN - which then could produce out-of-bound offsets.

(Note that the explicit NaN behavior changes for min/max on x86 sse don't
result in actual changes in the generated jit code, but may on other
architectures. Found by looking through all the wrap functions.)

This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94955

No piglit changes.

(v2: fix min/max typo in coord_mirror, add comment)

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>

Tested-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-04-26 04:55:37 +02:00
Dave Airlie
d8edc3e97c radeonsi: fix missing include for Elements.
Since u_blitter.h no longer defines this.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-04-26 09:36:23 +10:00
Samuel Pitoiset
d12c3b02ff nvc0: bump the amount of shared memory per MP on Maxwell
According to the CUDA compute capability version, GM10x can expose
64KB of shared memory while GM20x can use 96KB.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-04-26 00:32:25 +02:00
Dave Airlie
5b6a1aee46 r600: fix missing include for Elements macro
This got removed from u_blitter.h and we were taking it from
there, this should just move to ARRAY_SIZE eventually.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-04-26 08:01:01 +10:00
Samuel Pitoiset
725431a5db gm107/ir: s/invalid load/invalid store/
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-04-25 23:55:52 +02:00
Rob Clark
d2fcd0ce38 freedreno/a3xx: remove unused fxn
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 17:10:14 -04:00
Rob Clark
8fe2076243 freedreno/ir3: convert over to ralloc
The home-grown heap scheme (which is ultra-simple but probably not good
to always allocate and memset such a chunk of memory up front) was a
remnant of fdre (where the ir originally came from).  But since we have
ralloc in mesa, lets just use that instead.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 17:09:09 -04:00
Rob Clark
2c8674f5a9 freedreno: honor handle->offset
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:22 -04:00
Rob Clark
dfd23abdcc freedreno: disallow cat4 immed src
Normally this would never happen (constant-propagation in NIR would
eliminate the instruction), except it does happen for 'undef' which
we turn into immed 0.0 for bookkeeping purposes.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:21 -04:00
Rob Clark
76c6cdd36a freedreno/a4xx: add render-target formats
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:21 -04:00
Rob Clark
7add166a5c freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:21 -04:00
Rob Clark
edcc6ce75d freedreno: reduce line width for deqp further
See a7eb12d0.. but that wasn't restrictive enough.  Fixes
dEQP-GLES3.functional.rasterization.primitives.line_strip_wide, and
similar

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:21 -04:00
Rob Clark
4610e5ef28 freedreno/ir3: fix sin/cos
We seem to need range reduction to get sane results.  Fixes glmark2
jellyfish bench, and a whole bunch of
dEQP-GLES3.functional.shaders.builtin_functions.precision.{sin,cos,tan}.*

v2: squashed in android build fixes from Rob Herring

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-25 16:16:21 -04:00
Charmaine Lee
c4cb879f00 svga: eliminiate unnecessary constant buffer updates
Currently if the texture binding is changed, emit_fs_consts()
is triggered to update texture scaling factor for
rectangle texture or texture buffer size in the constant buffer.
But the update is only relevant if the texture binding includes
a rectangle texture or a texture buffer.

To eliminate the unnecessary constant buffer updates due to other texture
binding changes, a new flag SVGA_NEW_TEXTURE_CONSTS will be used
to trigger fragment shader constant buffer update when a rectangle texture
or a texture buffer is bound.

With this patch, the number of constant buffer updates in Lightsmark2008
reduces from hundreds per frame to about 28 per frame.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-25 12:59:29 -06:00
Charmaine Lee
686cd3c606 svga: mark the texture dirty for write transfer map only
Instead of unconditionally mark the texture subresource dirty at transfer map,
we'll set the dirty bit for write transfer only.

Tested with lightsmark2008 and glretrace.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-25 12:59:29 -06:00
Charmaine Lee
676931640f svga: fix assert with PIPE_QUERY_OCCLUSION_PREDICATE for non-vgpu10
With this patch, when running in hardware version 11, we'll use
SVGA3D_QUERYTYPE_OCCLUSION query type for PIPE_QUERY_OCCLUSION_PREDICATE
and return TRUE if samples-passed count is greater than 0.

Fixes glretrace/solidworks2012_viewport running in hardware version 11.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-25 12:59:29 -06:00
Charmaine Lee
d7a6c1a476 svga: minimize surface flush
Currently, we always do a surface flush when we try to establish
a synchronized write transfer map. But if the subresource has not
been modified, we can skip the surface flush. In other words,
we only need to do a surface flush if the to-be-mapped subresource
has been modified in this command buffer.

With this patch, lightsmark2008 shows about 15% performance improvement.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-04-25 12:59:29 -06:00
Brian Paul
63df017fda util/blitter: use ARRAY_SIZE macro
And remove local definition of Elements() macro.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-25 12:59:29 -06:00
Brian Paul
e0184b3995 svga: s/Elements/ARRAY_SIZE/
Standardize on the later macro rather than a mix of both.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-04-25 12:59:29 -06:00
Brian Paul
77e4b41671 svga: whitespace and formatting fixes in svga_pipe_rasterizer.c 2016-04-25 12:59:29 -06:00
Brian Paul
25e0d3659f svga: whitespace and formatting fixes in svga_pipe_depthstencil.c 2016-04-25 12:59:29 -06:00
Brian Paul
595fbc8dee svga: whitespace and formatting fixes in svga_pipe_sampler.c 2016-04-25 12:59:29 -06:00
Brian Paul
1db8313168 gallium/util: initialize pipe_framebuffer_state to zeros
To silence a valgrind uninitialized memory warning.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94955
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-04-25 12:59:29 -06:00
Brian Paul
1e990978ee util/cache: add comments, fix formatting 2016-04-25 12:59:29 -06:00
Brian Paul
464d6080c6 svga: separate HUD counters for state objects
Count depth/stencil, blend, sampler, etc. state objects separately
but just report the sum for the HUD.  This change lets us use gdb to
see the breakdown of state objects in more detail.

Also, count sampler views too.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-04-25 09:45:16 -06:00
Robert Foss
b87856d25d st/omx: Fix resource leak on OMX_ErrorNone
Avoid leaking buffer allocated for task if an error has occured.

Coverity id: 1213929
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-04-25 15:09:37 +01:00
Grazvydas Ignotas
dc732a8ef2 gallium: use unreachable instead of asserts
Avoids warnings in release builds.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-04-25 12:23:34 +02:00
Grazvydas Ignotas
cbb0d4ad75 gallium: fix warnings in release build
Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-04-25 12:23:21 +02:00
Hans de Goede
787a53988c nouveau: codegen: combineLd/St do not combine indirect loads
combineLd/St would combine, i.e. :

st  u32 # g[$r2+0x0] $r2
st  u32 # g[$r2+0x4] $r3

into:

st  u64 # g[$r2+0x0] $r2d

But this is only valid if r2 contains an 8 byte aligned address,
which is not guaranteed for compute shaders

This commit checks for src0 dim 0 not being indirect when combining
loads / stores as combining indirect loads / stores may break alignment
rules.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-04-25 11:45:07 +02:00
Rob Clark
0831eb94b9 freedreno/ir3: relax restriction in grouping
Currently we were two restrictive, and would insert an output move in
cases like: MOV OUT[0], IN[0].xyzw

Loosen the restriction to allow the current instruction to appear in the
neighbor list but only at it's current possition.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
36c9ea6e79 freedreno/ir3: fix small memory leak
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
610837fb98 freedreno/ir3: fix small RA bug
Normally the offset in the group would be the same, but not always.  For
example, in a sam(w) which only writes the 4th component.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
adf795432f freedreno/a4xx: better workaround for astc+srgb
This *seems* like a hw bug, and maybe only applies to certain a4xx
variants/revisions.  But setting the SRGB bit in sampler view state
(texconst0) causes invalid alpha for ASTC textures.  Work around this
setting up a second texture state and using that to sample alpha
separately.

This way, srgb->linear conversion happens in hw *prior* to
interpolation.

This fixes 546 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb*

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
a148300b13 Revert "freedreno/a4xx: lower srgb in shader for astc textures"
Better workaround in the following patch.

This reverts commit 899bd63ace.
2016-04-24 13:40:57 -04:00
Rob Clark
19118e6f47 freedreno/a4xx: blend state no longer depends on fb state
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00