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Author SHA1 Message Date
Gert Wollny
1dca2b8ae9 r600/sfn: Make sure texture lowering is done in the right order 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
ed6204eb06 r600/sfn: only use 3 channels on Cayman for trans ops 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
260cddf9ec r600/sfn: Handle shifts on Cayman 
Fixes: 00599f6e71
  r600/sfn: Schedule shift instruction on R600 in t-slot

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
2fbcd3d4a9 r600/sfn: fix some channel pinning 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
56ded410af r600/sfn: Add a free-channel mask when testing whether a register can switch channel 
This should avoid making 4 slot ops out of 3-slot ops on Cayman

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
668167aac1 r600/sfn: VS inputs are effectively SSA 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
f3415cb26a r600/sfn: copy propagate register load chains 
NIR sometimes produces load chains like

  r0 mov value
  r1 mov r0
  r2 mov r1

Add copy propagation for these cases

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
1852f1e328 r600/sfn: drop some unused code 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
c0b6c59e08 r600/sfn: Copy propagate into TEX source 
This is possible if all register values are actually from the same
register ID.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
5416d1bc4b r600/sfn: Don't assert when setting one value 
Instead add a method to validate the vec4 registers

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
4a505609e4 r600/sfn: Add an easy access to get an instruction as ALU 
This is used often and makes sense not to be implemented as
a visitor.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
a7c6a7e345 r600/sfn: Don't allocate un-used components in texture ops 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
5241568641 r600/sfn: print tex prepare instructions 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
c23604324b r600/sfn: copy-propagate single source texture values 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
1fc76aae10 r600/sfn: lower txf_ms in nir 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:09 +00:00
Gert Wollny
173d62fc16 r600/sfn: lower txd to backend in nir 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:08 +00:00
Gert Wollny
02bb506c54 r600/sfn: Lower tex,txl,txb and txf to backend 
This cleans up the texture code a bit and also gives
more opportunities for optimization in NIR.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
 2022-09-16 15:43:08 +00:00
Adam Jackson
a6483f0434 egl/dri2: Fix some thinkos in old context release 
All of the objects here should be relative to the old context / display
/ surfaces. Calling disp->unbindContext() on a context that disp did not
create is likely to go poorly.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18586>
 2022-09-16 14:23:47 +00:00
Adam Jackson
7a744aa318 egl/dri2: Fix a typo in a comment 
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18586>
 2022-09-16 14:23:47 +00:00
Adam Jackson
6c6a37ef94 egl/dri2: Respect the arguments to dri2_set_blob_cache_funcs 
This is no functional change, since this is effectively what the caller
is passing in, but it's still a layering violation.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18586>
 2022-09-16 14:23:47 +00:00
Adam Jackson
14c6f716b4 nouveau: const cleanup 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18586>
 2022-09-16 14:23:47 +00:00
Mike Blumenkrantz
3ac0706aa8 zink: export PIPE_CAP_SHADER_ATOMIC_INT64 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18144>
 2022-09-16 13:53:10 +00:00
Mike Blumenkrantz
c32f046ab6 zink: export PIPE_CAP_IMAGE_ATOMIC_FLOAT_ADD 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18144>
 2022-09-16 13:53:10 +00:00
Mike Blumenkrantz
c212a00ebf zink: handle 64bit float atomics 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18144>
 2022-09-16 13:53:10 +00:00
Mike Blumenkrantz
99a4a9c6ff zink: fix atomic ssbo indexing with non-32bit values 
this has to adjust using dest size, not hardcoded as uint32

Fixes: 5a95c6b328 ("zink: rewrite atomic ssbo intrinsics as atomic derefs")

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18144>
 2022-09-16 13:53:10 +00:00
Mike Blumenkrantz
9016943185 zink: emit Aliased decoration for aliased bo descriptors 
this is required any time two variables point to the same descriptor,
as is needed when multiple bitsizes are used

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18144>
 2022-09-16 13:53:10 +00:00
Mike Blumenkrantz
e32afce507 zink: simplify ntv shader descriptor emission 
these can be emitted directly

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18144>
 2022-09-16 13:53:10 +00:00
Mike Blumenkrantz
99ef2c9a1b zink: always set var used by get_ssbo_size to the 32bit var 
avoid depending on iteration ordering

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18144>
 2022-09-16 13:53:10 +00:00
Mike Blumenkrantz
86e635d6de zink: remove special-casing for 64bit runtime array emission 
this should be fine normally

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18144>
 2022-09-16 13:53:10 +00:00
Mike Blumenkrantz
96be036a6b zink: uncap ssbo size 
since the transition to UINT pipe cap, this no longer needs to be
restricted to appease gallium

fixes #7103

cc: mesa-stable

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18144>
 2022-09-16 13:53:10 +00:00
Rhys Perry
e122d95d73 radv: remove unnecessary .align_mul=4 
The builders can pick a default using the component size.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18465>
 2022-09-16 13:19:55 +00:00
Rhys Perry
ee1a75bd74 radv: use nir_ubfe_imm 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18465>
 2022-09-16 13:19:55 +00:00
Rhys Perry
272d37fa72 radv: shrink zero-initialization in vkCmdSetVertexInputEXT 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18465>
 2022-09-16 13:19:55 +00:00
Rhys Perry
891cb799aa radv: disable EXT_vertex_input_dynamic_state when using DGC 
This simplifies the DGC path and removes some untested code. The only user
of the partial DGC implementation (vkd3d-proton) doesn't use
EXT_vertex_input_dynamic_state.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18465>
 2022-09-16 13:19:55 +00:00
Rajnesh Kanwal
04dc963cd6 pvr: Implement vkCmdWaitEvents2 API. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18612>
 2022-09-16 13:02:30 +00:00
Rajnesh Kanwal
1c68620782 pvr: Implement vkCmdResetEvent2 API. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18612>
 2022-09-16 13:02:30 +00:00
Rajnesh Kanwal
de1da8fa76 pvr: Implement vkCmdSetEvent2 API. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18612>
 2022-09-16 13:02:30 +00:00
Rajnesh Kanwal
1b94dfd4b2 pvr: Implement vkCreateEvent and vkDestroyEvent APIs. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18612>
 2022-09-16 13:02:30 +00:00
Karmjit Mahil
def3b88da5 pvr: Add basic skeleton for event sub cmd. 
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Sarah Walker <Sarah.Walker@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18612>
 2022-09-16 13:02:30 +00:00
Samuel Pitoiset
299d294304 Revert "radv: upload the PS epilog in the existing pipeline BO" 
This is completely broken because the PS epilog has refcount and
radv_upload_shaders() updates its VA.

This reverts commit 7c34b31db2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18632>
 2022-09-16 11:38:28 +00:00
Iago Toral Quiroga
0fc38b358b v3dv: fix program id for binning shaders 
We had a comment stating that we were using different program ids for render
and binning but this isn't true. We were only assigning ids to the render
stages and then we would create the binning stages and not assign a program id
to them at all, so they would remain with a program id of 0.

This change removes the comment and makes sure we assign the same program
id to the binning and render stages of the pipeline, which makes it a lot
easier to match render and binning shaders when debugging.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18630>
 2022-09-16 10:11:06 +00:00
Qiang Yu
074f3216f2 ac/nir/ngg: support gs streamout 
Port from radeonsi.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
3fe8f88124 ac/nir/ngg: support multi stream per output slot for gs 
radeonsi may pack multi stream output to same slot.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
c25564b552 ac/nir/ngg: ngg_gs_load_out_vtx_primflag support stream 
Streamout need primflag for any stream.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
5ec79f9899 ac/nir/ngg: nogs support streamout 
Port from radeonsi.

Works on both GFX11 and GFX10. Although GFX10 can do atomic
GDS add on all threads, now we just disable the NGG streamout
for GFX10, so it's OK.

There's a difference for the GFX11 implementation with radeonsi
that we do all 4 buffer/stream info calc on a single thread.
It's just because this is simple, we need to update GDS on a
single thread anyway, and streamout is not that performance
critical to loss a small amount of instruction. We may change
to a better implementation when using register based streamout.

When streamout enabled, ES threads need to save all vertex
attributes to LDS besides position. This is because we don't
know where in the streamout buffer to export the attributes to
and wheter there are space in the streamout buffer.

Streamout is done in primitives, so we need to check if there
is space and where the current primitive should be written to
by GDS atomic add, then in GS threads do the streamout.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
30c7608516 ac/nir/ngg: cleanup prim id to prepare for streamout 
Streamout also need barrier after culling, so move the
prim id barrier up to after culling.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
6762bc8bd6 ac/llvm: implement nir_intrinsic_ordered_xfb_counter_add_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
4e06a8f15e nir: add nir_intrinsic_ordered_xfb_counter_add_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
1119e06a45 nir,ac/llvm: add nir_intrinsic_load_ordered_id_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00
Qiang Yu
5c2d710064 nir: add nir_intrinsic_load_streamout_buffer_amd 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17654>
 2022-09-16 08:51:28 +00:00