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radv: shrink zero-initialization in vkCmdSetVertexInputEXT
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18465>
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1 changed files with 18 additions and 1 deletions
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@ -3618,6 +3618,16 @@ radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer,
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unsigned i = u_bit_scan(&mask);
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uint32_t *desc = &((uint32_t *)vb_ptr)[desc_index++ * 4];
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uint32_t offset, rsrc_word3;
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if (vs_state && !(vs_state->attribute_mask & BITFIELD_BIT(i))) {
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/* No vertex attribute description given: assume that the shader doesn't use this
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* location (vb_desc_usage_mask can be larger than attribute usage) and use a null
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* descriptor to avoid hangs (prologs load all attributes, even if there are holes).
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*/
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memset(desc, 0, 4 * 4);
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continue;
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}
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unsigned binding =
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vs_state ? cmd_buffer->state.dynamic_vs_input.bindings[i]
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: (pipeline->use_per_attribute_vb_descs ? pipeline->attrib_bindings[i] : i);
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@ -5656,7 +5666,14 @@ radv_CmdSetVertexInputEXT(VkCommandBuffer commandBuffer, uint32_t vertexBindingD
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cmd_buffer->state.vbo_misaligned_mask = 0;
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cmd_buffer->state.vbo_misaligned_mask_invalid = 0;
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memset(state, 0, sizeof(*state));
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state->attribute_mask = 0;
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state->instance_rate_inputs = 0;
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state->nontrivial_divisors = 0;
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state->zero_divisors = 0;
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state->post_shuffle = 0;
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state->alpha_adjust_lo = 0;
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state->alpha_adjust_hi = 0;
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state->nontrivial_formats = 0;
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state->bindings_match_attrib = true;
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enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level;
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