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r600/sfn: fix some channel pinning

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Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
This commit is contained in:
Gert Wollny 2022-09-14 19:55:16 +02:00 • committed by Marge Bot
parent 56ded410af
commit 2fbcd3d4a9
3 changed files with 12 additions and 10 deletions
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12
src/gallium/drivers/r600/sfn/sfn_instr_mem.cpp
View file

@ -603,7 +603,7 @@ bool RatInstr::emit_ssbo_atomic_op(nir_intrinsic_instr *intr, Shader& shader)
auto coord_orig = vf.src(intr->src[1], 0);
auto coord = vf.temp_register(0);
auto data_vec4 = vf.temp_vec4(pin_group, {0,1,2,3});
auto data_vec4 = vf.temp_vec4(pin_chgr, {0,1,2,3});
shader.emit_instruction(new AluInstr(op2_lshr_int, coord, coord_orig, vf.literal(2), AluInstr::last_write));
@ -619,7 +619,7 @@ bool RatInstr::emit_ssbo_atomic_op(nir_intrinsic_instr *intr, Shader& shader)
}
RegisterVec4 out_vec(coord, coord, coord, coord, pin_group);
RegisterVec4 out_vec(coord, coord, coord, coord, pin_chgr);
auto atomic = new RatInstr(cf_mem_rat, opcode, data_vec4, out_vec, imageid + shader.ssbo_image_offset(),
image_offset, 1, 0xf, 0);
@ -677,10 +677,10 @@ bool RatInstr::emit_image_store(nir_intrinsic_instr *intrin, Shader& shader)
auto coord_load = vf.src_vec4(intrin->src[1], pin_chan);
auto coord = vf.temp_vec4(pin_group);
auto coord = vf.temp_vec4(pin_chgr);
auto value_load = vf.src_vec4(intrin->src[3], pin_chan);
auto value = vf.temp_vec4(pin_group);
auto value = vf.temp_vec4(pin_chgr);
RegisterVec4::Swizzle swizzle = {0,1,2,3};
if (nir_intrinsic_image_dim(intrin) == GLSL_SAMPLER_DIM_1D &&
@ -718,9 +718,9 @@ bool RatInstr::emit_image_load_or_atomic(nir_intrinsic_instr *intrin, Shader& sh
get_rat_opcode_wo(intrin->intrinsic, PIPE_FORMAT_R32_UINT);
auto coord_orig = vf.src_vec4(intrin->src[1], pin_chan);
auto coord = vf.temp_vec4(pin_group);
auto coord = vf.temp_vec4(pin_chgr);
auto data_vec4 = vf.temp_vec4(pin_group, {0,1,2,3});
auto data_vec4 = vf.temp_vec4(pin_chgr, {0,1,2,3});
RegisterVec4::Swizzle swizzle = {0,1,2,3};
if (nir_intrinsic_image_dim(intrin) == GLSL_SAMPLER_DIM_1D &&

8
src/gallium/drivers/r600/sfn/sfn_shader_gs.cpp
View file

@ -261,12 +261,12 @@ bool GeometryShader::store_output(nir_intrinsic_instr* instr)
src_swz[i] = (1 << i) & (write_mask << shift) ? i - shift: 7;
}
auto out_value = value_factory().src_vec4(instr->src[0], pin_group, src_swz);
auto out_value = value_factory().src_vec4(instr->src[0], pin_free, src_swz);
AluInstr *ir = nullptr;
if (m_streamout_data[location]) {
const auto& value = m_streamout_data[location]->value();
auto tmp = value_factory().temp_vec4(pin_group);
auto tmp = value_factory().temp_vec4(pin_chgr);
for (unsigned i = 0; i < 4 - shift; ++i) {
if (!(write_mask & (1 << i)))
continue;
@ -296,7 +296,7 @@ bool GeometryShader::store_output(nir_intrinsic_instr* instr)
}
if (need_copy) {
auto tmp = value_factory().temp_vec4(pin_group);
auto tmp = value_factory().temp_vec4(pin_chgr);
for (unsigned i = 0; i < 4 - shift; ++i) {
if (out_value[i]->chan() < 4) {
ir = new AluInstr(op1_mov, tmp[i], out_value[i], AluInstr::write);
@ -308,6 +308,8 @@ bool GeometryShader::store_output(nir_intrinsic_instr* instr)
4 * driver_location,
instr->num_components, m_export_base[0]);
} else {
for (auto i = 0; i < 4; ++i)
out_value[i]->set_pin(pin_chgr);
m_streamout_data[location] = new MemRingOutInstr(cf_mem_ring, MemRingOutInstr::mem_write_ind, out_value,
4 * driver_location,
instr->num_components, m_export_base[0]);

2
src/gallium/drivers/r600/sfn/sfn_shader_vs.cpp
View file

@ -613,7 +613,7 @@ bool VertexExportForGS::do_store_output(const store_loc &store_info, nir_intrins
for (int i = 0; i < 4; ++i)
src_swz[i] = i < instr.num_components ? i : 7;
auto value = m_parent->value_factory().temp_vec4(pin_group, src_swz);
auto value = m_parent->value_factory().temp_vec4(pin_chgr, src_swz);
AluInstr *ir = nullptr;
for (unsigned int i = 0; i < instr.num_components ; ++i) {