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r600/sfn: lower txf_ms in nir
Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
This commit is contained in:
Gert Wollny
Marge Bot
parent
173d62fc16
commit
1fc76aae10
3 changed files with 80 additions and 137 deletions
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@ -346,11 +346,6 @@ bool TexInstr::from_nir(nir_tex_instr *tex, Shader& shader)
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return emit_tex_lod(tex, src, shader);
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case nir_texop_query_levels:
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return emit_tex_txs(tex, src, {3,7,7,7}, shader);
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case nir_texop_txf_ms:
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if (shader.chip_class() < ISA_CC_EVERGREEN)
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return emit_tex_tex_ms_direct(tex, src, shader);
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else
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return emit_tex_tex_ms(tex, src, shader);
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case nir_texop_tg4:
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return emit_tex_tg4(tex, src, shader);
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case nir_texop_texture_samples:
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@ -395,6 +390,7 @@ bool TexInstr::emit_lowered_tex(nir_tex_instr* tex, Inputs& src, Shader& shader)
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auto params = nir_src_as_const_value(*src.backend2);
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int32_t coord_mask = params[0].i32;
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int32_t flags = params[1].i32;
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int32_t inst_mode = params[2].i32;
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TexInstr *grad[2] = {nullptr, nullptr};
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@ -437,6 +433,7 @@ bool TexInstr::emit_lowered_tex(nir_tex_instr* tex, Inputs& src, Shader& shader)
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}
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irt->set_coord_offsets(src.offset);
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irt->set_inst_mode(inst_mode);
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shader.emit_instruction(irt);
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return true;
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@ -486,134 +483,6 @@ bool TexInstr::emit_buf_txf(nir_tex_instr *tex, Inputs& src, Shader& shader)
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return true;
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}
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bool TexInstr::emit_tex_tex_ms_direct(nir_tex_instr *tex, Inputs& src, Shader& shader)
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{
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assert(tex->src[0].src.is_ssa);
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auto& vf = shader.value_factory();
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r600::sfn_log << SfnLog::instr << "emit '"
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<< *reinterpret_cast<nir_instr*>(tex)
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<< "' (" << __func__ << ")\n";
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auto sampler = get_sampler_id(tex->sampler_index, src.sampler_deref);
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assert(!sampler.indirect && "Indirect sampler selection not yet supported");
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auto temp2 = vf.temp_vec4(pin_group);
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for (unsigned i = 0; i < tex->coord_components; ++i) {
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unsigned k = i;
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if (tex->is_array && tex->sampler_dim == GLSL_SAMPLER_DIM_1D && i == 1)
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k = 2;
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shader.emit_instruction(new AluInstr(op1_mov, temp2[k],
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src.coord[k], AluInstr::write));
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}
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shader.emit_instruction(new AluInstr(op1_mov, temp2[3], src.ms_index,
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AluInstr::last_write));
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auto dst = vf.dest_vec4(tex->dest, pin_group);
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/* txf doesn't need rounding for the array index, but 1D has the array index
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* in the z component */
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auto tex_ir = new TexInstr(ld, dst, {0,1,2,3}, temp2,
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sampler.id,
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sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
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shader.emit_instruction(tex_ir);
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return true;
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}
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bool TexInstr::emit_tex_tex_ms(nir_tex_instr *tex, Inputs& src, Shader& shader)
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{
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assert(tex->src[0].src.is_ssa);
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auto& vf = shader.value_factory();
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r600::sfn_log << SfnLog::instr << "emit '"
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<< *reinterpret_cast<nir_instr*>(tex)
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<< "' (" << __func__ << ")\n";
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auto sampler = get_sampler_id(tex->sampler_index, src.sampler_deref);
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assert(!sampler.indirect && "Indirect sampler selection not yet supported");
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auto sample_id_dest = vf.temp_vec4(pin_group);
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RegisterVec4::Swizzle dest_swz = {0,7,7,7};
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auto temp1 = vf.temp_vec4(pin_group);
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for (unsigned i = 0; i < tex->coord_components; ++i) {
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unsigned k = i;
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if (tex->is_array && tex->sampler_dim == GLSL_SAMPLER_DIM_1D && i == 1)
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k = 2;
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if (src.offset && i < src.offset->ssa->num_components)
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shader.emit_instruction(new AluInstr(op2_add_int, temp1[k],
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src.coord[i],
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vf.src(*src.offset, i),
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AluInstr::write));
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else
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shader.emit_instruction(new AluInstr(op1_mov, temp1[k],
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src.coord[i], AluInstr::write));
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}
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shader.emit_instruction(new AluInstr(op1_mov, temp1[3],
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src.ms_index, AluInstr::last_write));
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auto tex_sample_id_ir = new TexInstr(ld, sample_id_dest, dest_swz, temp1,
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sampler.id,
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sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
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tex_sample_id_ir->set_tex_flag(x_unnormalized);
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tex_sample_id_ir->set_tex_flag(y_unnormalized);
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tex_sample_id_ir->set_tex_flag(z_unnormalized);
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tex_sample_id_ir->set_tex_flag(w_unnormalized);
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tex_sample_id_ir->set_inst_mode(1);
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shader.emit_instruction(tex_sample_id_ir);
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Register *sample_id_dest_reg = sample_id_dest[0];
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if (!src.ms_index->as_inline_const() ||
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src.ms_index->as_inline_const()->sel() != ALU_SRC_0) {
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auto help = vf.temp_register();
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shader.emit_instruction(new AluInstr(op2_lshl_int, help,
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src.ms_index, vf.literal(2),
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AluInstr::last_write));
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sample_id_dest_reg = vf.temp_register();
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shader.emit_instruction(new AluInstr(op2_lshr_int, sample_id_dest_reg,
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sample_id_dest[0], help,
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AluInstr::last_write));
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}
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auto temp2 = vf.temp_vec4(pin_group);
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for (unsigned i = 0; i < tex->coord_components; ++i) {
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unsigned k = i;
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if (tex->is_array && tex->sampler_dim == GLSL_SAMPLER_DIM_1D && i == 1)
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k = 2;
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shader.emit_instruction(new AluInstr(op1_mov, temp2[k],
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temp1[k], AluInstr::write));
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}
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shader.emit_instruction(new AluInstr(op2_and_int, temp2[3],
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sample_id_dest_reg, vf.literal(15),
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AluInstr::last_write));
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auto dst = vf.dest_vec4(tex->dest, pin_group);
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/* txf doesn't need rounding for the array index, but 1D has the array index
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* in the z component */
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auto tex_ir = new TexInstr(ld, dst, {0,1,2,3}, temp2,
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sampler.id,
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sampler.id + R600_MAX_CONST_BUFFERS, src.sampler_offset);
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shader.emit_instruction(tex_ir);
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return true;
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}
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bool TexInstr::emit_tex_texture_samples(nir_tex_instr* instr, Inputs& src, Shader& shader)
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{
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RegisterVec4 dest = shader.value_factory().dest_vec4(instr->dest, pin_chan);
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@ -994,6 +863,8 @@ private:
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nir_ssa_def *lower_tex(nir_tex_instr *tex);
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nir_ssa_def *lower_txf(nir_tex_instr *tex);
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nir_ssa_def *lower_txf_ms(nir_tex_instr *tex);
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nir_ssa_def *lower_txf_ms_direct(nir_tex_instr *tex);
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nir_ssa_def *prepare_coord(nir_tex_instr *tex,
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int &unnormalized_mask,
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@ -1033,6 +904,7 @@ bool LowerTexToBackend::filter(const nir_instr *instr) const
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case nir_texop_txl:
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case nir_texop_txf:
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case nir_texop_txd:
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case nir_texop_txf_ms:
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break;
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default:
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return false;
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@ -1054,7 +926,11 @@ nir_ssa_def *LowerTexToBackend::lower(nir_instr *instr)
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return lower_tex(tex);
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case nir_texop_txf:
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return lower_txf(tex);
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case nir_texop_txf_ms:
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if (m_chip_class < EVERGREEN)
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return lower_txf_ms_direct(tex);
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else
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return lower_txf_ms(tex);
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default:
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return nullptr;
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}
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@ -1095,6 +971,73 @@ nir_ssa_def *LowerTexToBackend::lower_txf(nir_tex_instr *tex)
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return finalize(tex, backend1, backend2);
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}
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nir_ssa_def *LowerTexToBackend::lower_txf_ms(nir_tex_instr *tex)
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{
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std::array<nir_ssa_def *, 4> new_coord = {
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nullptr,
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nullptr,
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nullptr,
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nullptr
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};
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get_src_coords(tex, new_coord, false);
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int ms_index = nir_tex_instr_src_index(tex, nir_tex_src_ms_index);
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new_coord[3] = tex->src[ms_index].src.ssa;
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int offset_index = nir_tex_instr_src_index(tex, nir_tex_src_offset);
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if (offset_index >= 0) {
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auto offset = tex->src[offset_index].src.ssa;
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for (int i = 0; i < offset->num_components; ++i) {
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new_coord[i] = nir_iadd(b, new_coord[i],
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nir_channel(b, offset, i));
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}
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}
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auto fetch_sample = nir_instr_as_tex(nir_instr_clone(b->shader, &tex->instr));
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nir_ssa_dest_init(&fetch_sample->instr, &fetch_sample->dest, 4, 32, "sample_index");
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int used_coord_mask = 0;
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nir_ssa_def *backend1 = prep_src(new_coord, used_coord_mask);
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nir_ssa_def *backend2 = nir_imm_ivec4(b, used_coord_mask, 0xf, 1, 0);
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nir_builder_instr_insert(b, &fetch_sample->instr);
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finalize(fetch_sample, backend1, backend2);
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new_coord[3] = nir_iand_imm(b,
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nir_ushr(b,
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nir_channel(b, &fetch_sample->dest.ssa, 0),
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nir_ishl_imm(b, new_coord[3], 2)
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), 15);
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nir_ssa_def *backend1b = prep_src(new_coord, used_coord_mask);
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nir_ssa_def *backend2b = nir_imm_ivec4(b, used_coord_mask, 0, 0, 0);
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return finalize(tex, backend1b, backend2b);
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}
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nir_ssa_def *LowerTexToBackend::lower_txf_ms_direct(nir_tex_instr *tex)
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{
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std::array<nir_ssa_def *, 4> new_coord = {
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nullptr,
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nullptr,
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nullptr,
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nullptr
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};
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get_src_coords(tex, new_coord, false);
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int ms_index = nir_tex_instr_src_index(tex, nir_tex_src_ms_index);
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new_coord[3] = tex->src[ms_index].src.ssa;
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int used_coord_mask = 0;
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nir_ssa_def *backend1 = prep_src(new_coord, used_coord_mask);
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nir_ssa_def *backend2 = nir_imm_ivec4(b, used_coord_mask, 0, 0, 0);
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return finalize(tex, backend1, backend2);
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}
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nir_ssa_def *LowerTexToBackend::finalize(nir_tex_instr *tex, nir_ssa_def *backend1,
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nir_ssa_def *backend2)
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{
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@ -1106,7 +1049,8 @@ nir_ssa_def *LowerTexToBackend::finalize(nir_tex_instr *tex, nir_ssa_def *backen
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nir_tex_src_coord,
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nir_tex_src_lod,
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nir_tex_src_bias,
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nir_tex_src_comparator
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nir_tex_src_comparator,
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nir_tex_src_ms_index
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};
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for (const auto type : cleanup) {
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@ -169,8 +169,6 @@ private:
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static auto prepare_source(nir_tex_instr *tex, const Inputs& inputs, Shader &shader) -> RegisterVec4;
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static bool emit_buf_txf(nir_tex_instr *tex, Inputs& src, Shader& shader);
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static bool emit_tex_tex_ms_direct(nir_tex_instr *tex, Inputs& src, Shader& shader);
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static bool emit_tex_tex_ms(nir_tex_instr *tex, Inputs& src, Shader& shader);
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static bool emit_tex_txs(nir_tex_instr *tex, Inputs& src,
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RegisterVec4::Swizzle dest_swz, Shader& shader);
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static bool emit_tex_lod(nir_tex_instr* tex, Inputs& src, Shader& shader);
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@ -520,6 +520,7 @@ bool simplify_source_vectors(Shader& sh)
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void SimplifySourceVecVisitor::visit(TexInstr *instr)
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{
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if (instr->opcode() != TexInstr::get_resinfo) {
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replace_src(instr, instr->src());
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}
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