fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-28 14:40:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1
119152 commits 64 branches 914 tags 1 GiB
Commit graph

531 commits

Author SHA1 Message Date
Marek Olšák
363b4027fc radeonsi: put up to 5 VBO descriptors into user SGPRs 
gfx6-8: 1 VBO descriptor in user SGPRs
gfx9-10: 5 VBO descriptors in user SGPRs

We no longer pull up to 5 VBO descriptors from GTT when SDMA is disabled.

Totals from affected shaders:
SGPRS: 1110528 -> 1170528 (5.40 %)
VGPRS: 952896 -> 951936 (-0.10 %)
Spilled SGPRs: 83 -> 61 (-26.51 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 23766296 -> 22843920 (-3.88 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 179344 -> 179344 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-13 15:57:07 -05:00
Marek Olšák
312e04689a radeonsi: don't allow draw calls with uninitialized VS inputs 
These always hang, because vertex buffer descriptors are not set up.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-13 15:57:07 -05:00
Marek Olšák
fd84e422b6 radeonsi: clean up messy si_emit_rasterizer_prim_state 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 15:48:49 -05:00
Marek Olšák
898c9cb797 radeonsi: fix context roll tracking in si_emit_shader_vs 
probably harmless, because we don't need to track context rolls on gfx10

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 15:48:39 -05:00
Marek Olšák
420fe1e7f9 radeonsi: remove TGSI 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-06 15:57:20 -05:00
Marek Olšák
e79f55ff86 radeonsi/gfx10: improve performance for TES using PrimID but not exporting it 
This field is really for the primitive export to the pixel shader.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-12-27 13:50:57 -05:00
Marek Olšák
aa3df12fc2 radeonsi/gfx10: enable NGG passthrough for eligible shaders 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-12-27 13:50:57 -05:00
Marek Olšák
aced18aa61 radeonsi/gfx10: simplify the tess_turns_off_ngg condition 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-12-10 16:32:36 -05:00
Marek Olšák
42f921387b radeonsi/gfx10: disable vertex grouping 
based on PAL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-12-10 16:32:34 -05:00
Marek Olšák
4675cb2019 radeonsi: initialize the per-context compiler on demand 
This takes a noticable amount of time in piglit and some tests don't
need it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-11-25 16:48:27 -05:00
Marek Olšák
3ef50b023e radeonsi/nir: fix compute shader crash due to nir_binary == NULL 
This partially reverts 8b30114dda.

Fixes: 8b30114dda "radeonsi/nir: call nir_serialize only once per shader"
 2019-11-08 16:47:59 -05:00
Marek Olšák
8b30114dda radeonsi/nir: call nir_serialize only once per shader 
We were calling it twice.

First serialize it, then use it to compute the cache key.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2019-11-08 15:30:28 -05:00
Marek Olšák
442ef8c3e3 radeonsi: keep serialized NIR instead of nir_shader in si_shader_selector 
This decreases memory usage, because serialized NIR is more compact.

The main shader part is compiled from nir_shader.
Monolithic shader variants are compiled from nir_binary.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2019-11-05 23:28:45 -05:00
Marek Olšák
62229e8949 radeonsi: use IR SHA1 as the cache key for the in-memory shader cache 
instead of using whole IR binaries. This saves some memory.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2019-11-05 23:28:42 -05:00
Marek Olšák
4d1e43badb radeonsi: initialize shader compilers in threads on demand 
It takes a noticable amount of time with piglit.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2019-10-28 21:36:18 -04:00
Marek Olšák
fff884e09d radeonsi/nir: implement pipe_screen::finalize_nir 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2019-10-23 21:12:52 -04:00
Marek Olšák
268e0e01f3 radeonsi/nir: simplify si_lower_nir signature 
just a cleanup
 2019-10-15 21:52:09 -04:00
Marek Olšák
dd4cc56ebd nir: add a strip parameter to nir_serialize 
so that drivers don't have to call nir_strip manually.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
 2019-10-10 15:47:07 -04:00
Marek Olšák
743a9d85e2 radeonsi: add FMASK slots for shader images (for MSAA images) 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-10-09 17:12:31 -04:00
Marek Olšák
eec7b0a865 radeonsi: use simple_mtx_t instead of mtx_t 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2019-10-07 20:05:07 -04:00
Timothy Arceri
896885025f util/u_queue: track job size and limit the size of queue growth 
When both UTIL_QUEUE_INIT_RESIZE_IF_FULL and
UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY are set, we can get into a
situation where the queue never executes and grows to a huge size
due to all other threads being busy.

This is the case with the shader cache when attempting to compile a
huge number of shaders up front. If all threads are busy compiling
shaders the cache queues memory use can climb into the many GBs
very fast.

The use of these two flags with the shader cache is intended to
allow shaders compiled at runtime to be compiled as fast as possible.
To avoid huge memory use but still allow the queue to perform
optimally in the run time compilation case, we now add the ability
to track memory consumed by the jobs in the queue and limit it to
a hardcoded 256MB which should be more than enough.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-09-19 15:03:27 +10:00
Marek Olšák
360cf3c4b0 radeonsi: fix scratch buffer WAVESIZE setting leading to corruption 
Cc: 19.2 19.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:52:32 -04:00
Marek Olšák
40e5ac45ae radeonsi: align scratch and ring buffer allocations for faster memory access 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:52:28 -04:00
Marek Olšák
d8f27552f4 radeonsi: consolidate determining VGPR_COMP_CNT for API VS 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Marek Olšák
4dde40908f radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flags 
We need two different values of the register, one for NGG and one for
legacy, in order to fix edge flags for the legacy pipeline.

Passing the ngg flag to emit_clip_regs would be too complicated,
so CONTEXT_REG_RMW is used for partial register updates.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Marek Olšák
1426acf9e7 radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variables 
It varies depending on si_shader_key::as_ngg.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Marek Olšák
28f44ee533 radeonsi/gfx10: fix InstanceID for legacy VS+GS 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Marek Olšák
e121d75de9 radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64 
Legacy GS only works with Wave64.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Marek Olšák
f34d023f1a radeonsi/gfx10: create the GS copy shader if using legacy streamout 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Marek Olšák
776f05a307 radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy streamout 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Marek Olšák
cab5b3861d radeonsi/gfx10: fix tessellation for the legacy pipeline 
ported from PAL

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Marek Olšák
a9bb566955 radeonsi: move some global shader cache flags to per-binary flags 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Marek Olšák
810846e157 radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the shader cache 
It could load an NGG shader when we want a legacy shader and vice versa.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-27 16:16:08 -04:00
Samuel Pitoiset
021feb1bf6 ac: add rbplus_allowed to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:41 +02:00
Samuel Pitoiset
c08401f035 ac: add has_distributed_tess to ac_gpu_info 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-27 08:04:11 +02:00
Marek Olšák
223b3174bd radeonsi/nir: always lower ballot masks as 64-bit, codegen handles it 
This fixes KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks.

This solution is better, because the IR isn't dependent on wave32.
 2019-08-19 17:23:38 -04:00
Marek Olšák
bdcbac9459 radeonsi: handle the use_ngg_streamout flag in si_update_ngg 2019-08-19 17:23:38 -04:00
Marek Olšák
a6b3ca1c70 radeonsi: move the tess factor ring size assertion to a place where it matters 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-19 17:23:38 -04:00
Marek Olšák
8ce4f9bbc3 radeonsi: remove the always_nir option 
tgsi_to_nir is no longer optional if NIR is enabled.
 2019-08-12 14:52:17 -04:00
Marek Olšák
6a2bdb8d01 gallium: add TGSI_PROPERTY_VS_BLIT_SGPRS_AMD for tgsi_to_nir 
needed by radeonsi NIR support
 2019-08-12 14:52:17 -04:00
Marek Olšák
91227a1e17 radeonsi/gfx10: add global use_ngg and use_ngg_streamout flags 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:09:02 -04:00
Marek Olšák
f064b530f6 radeonsi/gfx10: remove an obsolete VGT_REUSE_OFF workaround 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:09:01 -04:00
Marek Olšák
c5a6ecf61a radeonsi/gfx10: implement a bug workaround for GE_PC_ALLOC 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:08:58 -04:00
Marek Olšák
8f8c28767e radeonsi/gfx10: implement a bug workaround for NGG -> legacy transitions 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:08:57 -04:00
Marek Olšák
cb9d95623b radeonsi/gfx10: implement a GE bug workaround 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:08:56 -04:00
Marek Olšák
71b53020b7 radeonsi/gfx10: simplify NGG code in si_update_shaders 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:08:53 -04:00
Marek Olšák
a232f5e07c radeonsi/gfx10: fix input VGPRs for legacy VS 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:08:51 -04:00
Marek Olšák
8b8819e88a radeonsi: make sure that DSA state != NULL and remove all NULL checking 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:08:39 -04:00
Marek Olšák
b758eed9c3 radeonsi: make sure that blend state != NULL and remove all NULL checking 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:08:39 -04:00
Marek Olšák
e777720173 radeonsi/nir: lower PS inputs before scanning the shader 
Lowering PS inputs can eliminate some of them, which messes up
persp/linear barycentric coord usage info.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:08:46 -04:00