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radeonsi: clean up messy si_emit_rasterizer_prim_state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
This commit is contained in:
parent
b64a3240c2
commit
fd84e422b6
5 changed files with 30 additions and 39 deletions
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@ -438,9 +438,6 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
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ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
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ctx->last_prim = -1;
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ctx->last_multi_vgt_param = -1;
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ctx->last_rast_prim = -1;
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ctx->last_flatshade_first = -1;
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ctx->last_sc_line_stipple = ~0;
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ctx->last_vs_state = ~0;
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ctx->last_ls = NULL;
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ctx->last_tcs = NULL;
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@ -492,6 +489,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
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ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
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ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005;
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ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE] = 0xffff;
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ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_STIPPLE] = 0;
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ctx->tracked_regs.reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE] = 0x00000000;
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ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1] = 0x00000000;
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ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2] = 0x00000000;
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@ -525,11 +523,13 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
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ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM] = 0x00000000;
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ctx->tracked_regs.reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL] = 0x0000001e; /* From GFX8 */
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/* Set all saved registers state to saved. */
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/* Set all cleared context registers to saved. */
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ctx->tracked_regs.reg_saved = 0xffffffffffffffff;
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ctx->last_gs_out_prim = 0; /* cleared by CLEAR_STATE */
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} else {
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/* Set all saved registers state to unknown. */
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ctx->tracked_regs.reg_saved = 0;
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ctx->last_gs_out_prim = -1; /* unknown */
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}
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/* 0xffffffff is a impossible value to register SPI_PS_INPUT_CNTL_n */
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@ -1071,10 +1071,8 @@ struct si_context {
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int last_restart_index;
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int last_prim;
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int last_multi_vgt_param;
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int last_rast_prim;
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int last_flatshade_first;
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int last_gs_out_prim;
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int last_binning_enabled;
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unsigned last_sc_line_stipple;
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unsigned current_vs_state;
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unsigned last_vs_state;
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enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
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@ -311,6 +311,8 @@ enum si_tracked_reg {
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SI_TRACKED_PA_SC_CLIPRECT_RULE,
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SI_TRACKED_PA_SC_LINE_STIPPLE,
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SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
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SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 3 consecutive registers */
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@ -597,46 +597,37 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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enum pipe_prim_type rast_prim = sctx->current_rast_prim;
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struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
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bool use_ngg = sctx->screen->use_ngg;
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unsigned initial_cdw = cs->current.cdw;
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if (likely(rast_prim == sctx->last_rast_prim &&
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rs->pa_sc_line_stipple == sctx->last_sc_line_stipple &&
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(!use_ngg ||
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rs->flatshade_first == sctx->last_flatshade_first)))
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return;
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if (util_prim_is_lines(rast_prim)) {
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if (unlikely(si_is_line_stipple_enabled(sctx))) {
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/* For lines, reset the stipple pattern at each primitive. Otherwise,
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* reset the stipple pattern at each packet (line strips, line loops).
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*/
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radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
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rs->pa_sc_line_stipple |
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S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
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sctx->context_roll = true;
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unsigned value = rs->pa_sc_line_stipple |
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S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2);
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radeon_opt_set_context_reg(sctx, R_028A0C_PA_SC_LINE_STIPPLE,
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SI_TRACKED_PA_SC_LINE_STIPPLE, value);
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}
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unsigned gs_out = si_conv_prim_to_gs_out(sctx->current_rast_prim);
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unsigned gs_out_prim = si_conv_prim_to_gs_out(rast_prim);
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if (unlikely(gs_out_prim != sctx->last_gs_out_prim &&
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(sctx->ngg || sctx->gs_shader.cso))) {
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radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
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sctx->last_gs_out_prim = gs_out_prim;
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}
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if (rast_prim != sctx->last_rast_prim &&
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(sctx->ngg || sctx->gs_shader.cso)) {
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radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
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if (initial_cdw != cs->current.cdw)
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sctx->context_roll = true;
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if (use_ngg) {
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sctx->current_vs_state &= C_VS_STATE_OUTPRIM;
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sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out);
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}
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}
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if (sctx->ngg) {
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unsigned vtx_index = rs->flatshade_first ? 0 : gs_out_prim;
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if (use_ngg) {
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unsigned vtx_index = rs->flatshade_first ? 0 : gs_out;
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sctx->current_vs_state &= C_VS_STATE_PROVOKING_VTX_INDEX;
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sctx->current_vs_state |= S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
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sctx->current_vs_state &= C_VS_STATE_OUTPRIM &
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C_VS_STATE_PROVOKING_VTX_INDEX;
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sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out_prim) |
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S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
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}
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sctx->last_rast_prim = rast_prim;
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sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
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sctx->last_flatshade_first = rs->flatshade_first;
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}
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static void si_emit_vs_state(struct si_context *sctx,
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@ -3050,7 +3050,7 @@ bool si_update_ngg(struct si_context *sctx)
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sctx->flags |= SI_CONTEXT_VGT_FLUSH;
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sctx->ngg = new_ngg;
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sctx->last_rast_prim = -1; /* reset this so that it gets updated */
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sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
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return true;
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}
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return false;
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@ -3073,7 +3073,7 @@ static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
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sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
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si_update_common_shader_state(sctx);
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sctx->last_rast_prim = -1; /* reset this so that it gets updated */
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sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
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ngg_changed = si_update_ngg(sctx);
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if (ngg_changed || enable_changed)
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@ -3127,7 +3127,7 @@ static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
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si_update_tess_uses_prim_id(sctx);
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si_update_common_shader_state(sctx);
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sctx->last_rast_prim = -1; /* reset this so that it gets updated */
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sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
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bool ngg_changed = si_update_ngg(sctx);
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if (ngg_changed || enable_changed)
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