radeonsi: clean up messy si_emit_rasterizer_prim_state

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
This commit is contained in:
Marek Olšák 2020-01-06 22:10:04 -05:00
parent b64a3240c2
commit fd84e422b6
5 changed files with 30 additions and 39 deletions

View file

@ -438,9 +438,6 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
ctx->last_prim = -1;
ctx->last_multi_vgt_param = -1;
ctx->last_rast_prim = -1;
ctx->last_flatshade_first = -1;
ctx->last_sc_line_stipple = ~0;
ctx->last_vs_state = ~0;
ctx->last_ls = NULL;
ctx->last_tcs = NULL;
@ -492,6 +489,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE] = 0xffff;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_STIPPLE] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2] = 0x00000000;
@ -525,11 +523,13 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL] = 0x0000001e; /* From GFX8 */
/* Set all saved registers state to saved. */
/* Set all cleared context registers to saved. */
ctx->tracked_regs.reg_saved = 0xffffffffffffffff;
ctx->last_gs_out_prim = 0; /* cleared by CLEAR_STATE */
} else {
/* Set all saved registers state to unknown. */
ctx->tracked_regs.reg_saved = 0;
ctx->last_gs_out_prim = -1; /* unknown */
}
/* 0xffffffff is a impossible value to register SPI_PS_INPUT_CNTL_n */

View file

@ -1071,10 +1071,8 @@ struct si_context {
int last_restart_index;
int last_prim;
int last_multi_vgt_param;
int last_rast_prim;
int last_flatshade_first;
int last_gs_out_prim;
int last_binning_enabled;
unsigned last_sc_line_stipple;
unsigned current_vs_state;
unsigned last_vs_state;
enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */

View file

@ -311,6 +311,8 @@ enum si_tracked_reg {
SI_TRACKED_PA_SC_CLIPRECT_RULE,
SI_TRACKED_PA_SC_LINE_STIPPLE,
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 3 consecutive registers */

View file

@ -597,46 +597,37 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
struct radeon_cmdbuf *cs = sctx->gfx_cs;
enum pipe_prim_type rast_prim = sctx->current_rast_prim;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
bool use_ngg = sctx->screen->use_ngg;
unsigned initial_cdw = cs->current.cdw;
if (likely(rast_prim == sctx->last_rast_prim &&
rs->pa_sc_line_stipple == sctx->last_sc_line_stipple &&
(!use_ngg ||
rs->flatshade_first == sctx->last_flatshade_first)))
return;
if (util_prim_is_lines(rast_prim)) {
if (unlikely(si_is_line_stipple_enabled(sctx))) {
/* For lines, reset the stipple pattern at each primitive. Otherwise,
* reset the stipple pattern at each packet (line strips, line loops).
*/
radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
rs->pa_sc_line_stipple |
S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
sctx->context_roll = true;
unsigned value = rs->pa_sc_line_stipple |
S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2);
radeon_opt_set_context_reg(sctx, R_028A0C_PA_SC_LINE_STIPPLE,
SI_TRACKED_PA_SC_LINE_STIPPLE, value);
}
unsigned gs_out = si_conv_prim_to_gs_out(sctx->current_rast_prim);
unsigned gs_out_prim = si_conv_prim_to_gs_out(rast_prim);
if (unlikely(gs_out_prim != sctx->last_gs_out_prim &&
(sctx->ngg || sctx->gs_shader.cso))) {
radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
sctx->last_gs_out_prim = gs_out_prim;
}
if (rast_prim != sctx->last_rast_prim &&
(sctx->ngg || sctx->gs_shader.cso)) {
radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
if (initial_cdw != cs->current.cdw)
sctx->context_roll = true;
if (use_ngg) {
sctx->current_vs_state &= C_VS_STATE_OUTPRIM;
sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out);
}
}
if (sctx->ngg) {
unsigned vtx_index = rs->flatshade_first ? 0 : gs_out_prim;
if (use_ngg) {
unsigned vtx_index = rs->flatshade_first ? 0 : gs_out;
sctx->current_vs_state &= C_VS_STATE_PROVOKING_VTX_INDEX;
sctx->current_vs_state |= S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
sctx->current_vs_state &= C_VS_STATE_OUTPRIM &
C_VS_STATE_PROVOKING_VTX_INDEX;
sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out_prim) |
S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
}
sctx->last_rast_prim = rast_prim;
sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
sctx->last_flatshade_first = rs->flatshade_first;
}
static void si_emit_vs_state(struct si_context *sctx,

View file

@ -3050,7 +3050,7 @@ bool si_update_ngg(struct si_context *sctx)
sctx->flags |= SI_CONTEXT_VGT_FLUSH;
sctx->ngg = new_ngg;
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
return true;
}
return false;
@ -3073,7 +3073,7 @@ static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
si_update_common_shader_state(sctx);
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
ngg_changed = si_update_ngg(sctx);
if (ngg_changed || enable_changed)
@ -3127,7 +3127,7 @@ static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
si_update_tess_uses_prim_id(sctx);
si_update_common_shader_state(sctx);
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
bool ngg_changed = si_update_ngg(sctx);
if (ngg_changed || enable_changed)