Commit graph

63844 commits

Author SHA1 Message Date
Ilia Mirkin
1065aa92f4 nv50/ir: ignore bias for samplerCubeShadow on nv50
Unfortunately there's no good way to do this on the nv50 shader isa.
Dropping the bias seems preferable to doing the compare post-filtering.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
2014-07-08 00:14:33 -04:00
Ilia Mirkin
30d91e0eec nv50/ir: retrieve shadow compare from first arg
This can only happen with texture(samplerCubeShadow, bias), where the
compare will be in the first argument.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
2014-07-08 00:14:33 -04:00
Carl Worth
9007c4f9f4 docs: Import 10.2.3 release notes
And add a news item.
2014-07-07 16:28:37 -07:00
Matt Turner
f6db414f3c i965/fs: Disable unlit_centroid_workaround on Haswell.
Although the HSW PRM shows it, the BSpec lists this workaround as being
for Ivybridge only.

total instructions in shared programs: 1994951 -> 1993675 (-0.06%)
instructions in affected programs:     27325 -> 26049 (-4.67%)
2014-07-06 18:19:17 -07:00
Matt Turner
6f7c4a8d05 i965/vec4: Perform CSE on CMP(N) instructions.
Port of commit b16b3c87 to the vec4 code.

No shader-db improvements, but might as well. The fs backend saw an
improvement because it's scalar and multiple identical CMP instructions
were generated by the SEL peepholes.
2014-07-06 18:19:15 -07:00
Matt Turner
7921bf0062 i965/vec4: Don't emit null MOVs in CSE.
Port of commit 219b43c6 to the vec4 code.
2014-07-06 18:18:52 -07:00
Matt Turner
949991cc99 i965/vec4: Improve CSE performance by expiring some available expressions.
Port of commit 5daf867f to the vec4 code.
2014-07-06 18:18:52 -07:00
Kenneth Graunke
3c8dc48ad1 i965/vec4: Add basic common subexpression elimination.
[mattst88]: Modified to perform CSE on instructions with
            the same writemask. Offered no improvement before.

total instructions in shared programs: 1995633 -> 1995185 (-0.02%)
instructions in affected programs:     14410 -> 13962 (-3.11%)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-06 18:18:51 -07:00
Matt Turner
848fc7f710 i965: Fix warnings introduced in commit e24ef5ab.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-06 18:15:36 -07:00
Christian König
042b061fef gallium/radeon: use PRIX64 instead of PRIu64
We want hex values here, not decimals.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-07-06 13:28:04 +02:00
Matt Turner
1580865a8c i965: Move assembly annotation functions to intel_asm_annotation.c.
It's C. Compile it as such.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:30 -07:00
Matt Turner
423932791d i965: Rename intel_asm_printer -> intel_asm_annotation.
The #ifndef include guards already said the right thing :)

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:30 -07:00
Matt Turner
6d3e24a5c2 i965: Make backend_instruction usable from C.
With a hack to place an exec_node in the struct in C to be at the same
location as the inherited exec_node in C++.

Acked-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:30 -07:00
Matt Turner
0db30fcf89 i965/cfg: Make cfg_t usable from C.
Acked-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:30 -07:00
Matt Turner
857c06236c i965: Repack backend_instruction struct.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:30 -07:00
Matt Turner
ce706b4a9b i965: Make a brw_predicate enum.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:30 -07:00
Matt Turner
46e5b2a497 i965: Make a brw_conditional_mod enum.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:30 -07:00
Matt Turner
ab74a42eef i965: Move common fields into backend_instruction.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:30 -07:00
Matt Turner
3de11cacf0 i965: Use enum brw_reg_type for register types.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:30 -07:00
Matt Turner
34ef6a7651 i965: Move is_zero/one/null/accumulator into backend_reg.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:30 -07:00
Matt Turner
c019105f37 i965: Make a common backend_reg class.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:30 -07:00
Matt Turner
9377b189f7 i965: Drop imm union from visitor register classes.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:29 -07:00
Matt Turner
53992a102f i965: Use immediate storage in brw_reg for visitor regs.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-05 22:42:29 -07:00
Andreas Boll
45446efc30 docs: add news item for mesa-demos 8.2.0 release 2014-07-05 11:32:54 +02:00
Chris Forbes
4087d9ec0b glsl: Fix merging of layout(invocations) with other qualifiers
If another layout qualifier appeared to the left of `invocations` in the
GS input layout declaration, the invocation count would be dropped on
the floor.

Fixes the piglit tests:

spec/ARB_transform_feedback3/arb_transform_feedback3-ext_interleaved_two_bufs_gs_max
spec/ARB_gpu_shader5/arb_gpu_shader5-invocation-id
spec/ARB_gpu_shader5/compiler/correct-multiple-layout-qualifier-invocations.geom
spec/ARB_gpu_shader5/execution/invocations-conflicting

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-05 09:42:17 +12:00
Ilia Mirkin
9a37eb8adb nvc0: add a memory barrier when there are persistent UBOs
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-07-03 20:08:41 -04:00
Ilia Mirkin
5d4f5218bb nv50: do an explicit flush on draw when there are persistent buffers
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-07-03 20:01:07 -04:00
Ilia Mirkin
b2b7c65122 nv50: disable dedicated ubo upload method
The hardware allows multiple simultaneous renders with the same
memory-backed constbufs but with each invocation having different
values. However in order for that to work, the data has to be streamed
in via the right constbuf slot. We weren't doing that for UBOs.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.1" <mesa-stable@lists.freedesktop.org>
2014-07-03 20:01:06 -04:00
Ilia Mirkin
32b71246e7 gallium: rename PIPE_CAP_TGSI_VS_LAYER to also have _VIEWPORT
Now that this cap is used to determine the availability of both, adjust
its name to reflect the new reality.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-07-03 19:39:25 -04:00
Ilia Mirkin
0fb6f1bf1d mesa/st: enable AMD_vertex_shader_viewport_index
The assumption is that any driver capable of emitting layer from the
vertex shader and supporting viewports should be able to also handle
emitting viewport index from the vertex shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Tobias Droste <tdroste@gmx.de>
2014-07-03 19:39:25 -04:00
Ilia Mirkin
313acb3ffa r600g: allow vs to write to gl_ViewportIndex
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Tobias Droste <tdroste@gmx.de>
2014-07-03 19:39:25 -04:00
Thomas Hellstrom
556a415033 svga: Don't unnecessarily reemit BindGBShader commands v2
The Linux winsys can no longer relocate shader code, so avoid
reemitting BindGBShader commands. They are costly.

v2: Correctly handle errors from SVGA3D_BindGBShader()

Reported-by: Michael Banack <banackm@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2014-07-03 22:26:00 +02:00
Aaron Watry
824197efd5 radeon/llvm: Allocate space for kernel metadata operands
Previously, we were assuming that kernel metadata nodes only had 1 operand.

Kernels which have attributes can have more than 1, e.g.:
!0 = metadata !{void (i32 addrspace(1)*)* @testKernel, metadata !1}
!1 = metadata !{metadata !"work_group_size_hint", i32 4, i32 1, i32 1}

Attempting to get the kernel without the correct number of attributes led
to memory corruption and luxrays crashing out.

Fixes the cl/program/execute/attributes.cl piglit test.

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76223
CC: "10.2" <mesa-stable@lists.freedesktop.org>
2014-07-03 15:18:03 -05:00
Samuel Iglesias Gonsalvez
7f0420700c glsl: fix duplicated layout qualifier detection for GS
This patch fixes the duplicated layout qualifier detection
for geometry shader's layout qualifiers.

Also it makes the detection code more legible by defining
allowed_duplicates_mask variable.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80778
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-07-03 10:34:12 -07:00
Brian Paul
986adb9057 svga: add switch cases for PIPE_SHADER_CAP_DOUBLES
Signed-off-by: Brian Paul <brianp@vmware.com>
2014-07-03 08:25:50 -06:00
Thomas Hellstrom
35cf3831d7 st/xa: Don't close the drm fd on failure v2
If XA fails to initialize with pipe_loader enabled, the pipe_loader's
cleanup function will close the drm file descriptor. That's pretty bad
because the file descriptor will probably be the X server driver's only
connection to drm. Temporarily solve this by dup()'ing the file descriptor
before handing it over to the pipe loader.

This fixes freedesktop.org bugzilla bug #80645.

v2: Fix CC addresses.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2014-07-03 02:55:00 -07:00
Michel Dänzer
370184e813 Revert "radeonsi: Use dma_copy when possible for si_blit."
This reverts commit 5d5c20920e.

Caused visual corruption, see e.g.
https://bugs.freedesktop.org/show_bug.cgi?id=80827#c1
2014-07-03 11:17:38 +09:00
Ilia Mirkin
7666a9f4ae i965: expose AMD_vertex_shader_viewport_index on gen7+
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-07-02 21:59:41 -04:00
Ilia Mirkin
df61553070 glsl: add support for AMD_vertex_shader_viewport_index
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Tested-by: Tobias Droste <tdroste@gmx.de>
2014-07-02 21:59:38 -04:00
Ilia Mirkin
e593953b50 mesa: add support for AMD_vertex_shader_viewport_index
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Tested-by: Tobias Droste <tdroste@gmx.de>
2014-07-02 21:59:05 -04:00
Ilia Mirkin
6c544e5413 mesa/st: enable ARB_fragment_layer_viewport
If multiple viewports are supported, that implies the presence of a GS
and layered rendering, so we can enable ARB_fragment_layer_viewport as
well.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-07-02 20:20:53 -04:00
Eric Anholt
6ded75ed08 i965/gen6: Add a spec citation about push constant packet requirements.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-02 12:45:59 -07:00
Eric Anholt
e874274d08 i965: Add a comment about null renderbuffer surfaces and why they exist.
I noticed this when trying to find comments about pull constant buffers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-02 12:45:59 -07:00
Eric Anholt
489ec68554 i965: Update a ton of comments about constant buffers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-02 12:45:59 -07:00
Eric Anholt
e24ef5ab18 i965: Merge VS/GS and WM pull constant buffer upload paths.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-02 12:45:59 -07:00
Eric Anholt
34f4e614dd i965/gen6+: Merge VS/GS and WM push constant buffer upload paths.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-02 12:45:59 -07:00
Eric Anholt
c0f1929dd2 i965: Move dispatch_grf_start_reg and first_curbe_grf into stage_prog_data.
I wanted to access this value from stage-generic code, so stop storing it
under two different names.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-02 12:45:59 -07:00
Eric Anholt
5ba31c34d8 i965: Fix state flags for gen4/5 CURBE.
If we had some NOS affecting VS compilation that resulted in optimization
changing the set of constants to be uploaded, we might not have reuploaded
the constants.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-02 12:45:59 -07:00
Eric Anholt
a8330c343c i965: Remove a dead define.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-02 12:45:59 -07:00
Eric Anholt
c00d3bd59d i965: Reuse libdrm's header for AUB definitions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-02 12:45:59 -07:00