The idea behind this assert is that if a buffer is in
bufmgr->handle_table it's because it has been shared from i965 to the
outside. This is when we add the drm FD associated to this BO to
bo->exports.
But we also import buffer from the outside into i965 and those buffers
don't have an associated drm FD added to bo->exports.
If you import the same buffer more than once, you'll run into this
assert.
v2: Also drop assert from brw_bo_gem_create_from_name() (Ian)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 57e4d0aa1c ("i965: fix export of GEM handles")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10386>
(cherry picked from commit 03e97e94e7)
I mixed up the EXT and ARB version of the extensions; we actually do
require shaderStorageImageWriteWithoutFormat as well here.
Thanks to Ilia Mirkin for pointing this out.
It also seems I got really confused about what was required when writing
the docs, so let's fix that as well.
Fixes: 341332b23a ("zink: correct image cap checks")
Fixes: ecac7f3da1 ("docs: add missing zink-requirement")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10463>
(cherry picked from commit 4ec8533f69)
Conflicts:
docs/drivers/zink.rst
This fixes a bunch of MSAA related CTS regressions. This restores
previous behaviour on GFX9 but it should be fixed properly.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10374>
(cherry picked from commit a854a9fa62)
$(MESA_TOP)/src/compiler/nir include path is added
for both clarity and build errors preventive reasons
Cc: 21.0 21.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10443>
(cherry picked from commit a02328395d)
Since generated nir headers are included, it makes sense to include nir path
Fixes the following building error:
FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeonsi_intermediates/si_shader_nir.o
...
In file included from external/mesa/src/gallium/drivers/radeonsi/si_shader_nir.c:26:
external/mesa/src/amd/common/ac_nir.h:29:10: fatal error: 'nir.h' file not found
^~~~~~~
1 error generated.
Cc: 21.0 21.1 <mesa-stable@lists.freedesktop.org>
Fixes: 1c702a8239 ("ac: move ac_lower_indirect_derefs() outside of the LLVM dir")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10443>
(cherry picked from commit e213bfd330)
Don't setup inputs and outputs if we aren't using
load_input/store_output intrinsics. While it's mostly harmless, there
may be more outputs than expected which would lead to an oob write of
the outputs array when setting the register id to INVALID_REG.
Also be more paranoid with asserts to catch this.
Fixes: a6291b1 ("freedreno/ir3: rework setup_{input,output} to make struct varyings work")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7274>
(cherry picked from commit decfea2f4e)
This makes the vertex order of TRISTRIP and TRISTRIP_ADJ primitves
consistent between XFB output and GS input. Technically, the Vulkan
spec allows us to XFB out in whatever order we want but being consistent
with GS inputs is probably nicer to apps.
Fixes: 36ee2fd61c "anv: Implement the basic form of VK_EXT_transform_feedback"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10460>
(cherry picked from commit 22b8bcda2c)
PIPE_CAP_IMAGE_LOAD_FORMATTED doesn't depend on
shaderStorageImageExtendedFormats or
shaderStorageImageWriteWithoutFormat.
PIPE_SHADER_CAP_MAX_SHADER_IMAGES enables
GL_EXT_shader_image_load_store, which *does* require
shaderStorageImageExtendedFormats. Having
shaderStorageImageWriteWithoutFormat and
shaderStorageImageReadWithoutFormat isn't enough to support this.
It *might* be possible to lower extended formats to format-less
reads or writes, but we don't currently do that, so we should
just correct the test for now.
Fixes: 3f9a6d333b ("zink: export shader image caps using features")
Fixes: 5282210c0b ("zink: check correct caps for PIPE_CAP_IMAGE_LOAD_FORMATTED")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10456>
(cherry picked from commit 341332b23a)
The claim that we require vulkan memory model's MakeAvailable and
MakeVisible semantics for image writes isn't accurate. This would be
required *if* we were already using the Vulkan memory model.
But we're using the GLSL450 memory model in those cases, which has no
such requirements.
This means that any problems on RADV due to the lack of these semantics
are RADV bugs, and should be fixed in RADV instead.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10345>
(cherry picked from commit 95d9d811c9)
Modern shader APIs, like DX10 and GLSL 1.30, want min() and max() to
"cleanse" NaN. If one source is NaN, the other value should be chosen.
If both sources are NaN, the result may be either.
There are many cases where TGSI is generate from NIR, and many
optimizations in NIR expect this behavior. Not meeting these
expectations can lead to unexpected results.
Reviewed-by: Eric Anholt <eric@anholt.net>
Fixes: ffe58739da ("Softpipe: import TGSI tree. Not hooked-up yet.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10419>
(cherry picked from commit 939bf7a419)
Modern shader APIs, like DX10 and GLSL 1.30, want saturate or
clamp(..., 0.0, 1.0) to "cleanse" NaN. If the source is NaN, the
result should be zero.
There are many cases where TGSI is generate from NIR, and many
optimizations in NIR expect this behavior. Not meeting these
expectations can lead to unexpected results.
Reviewed-by: Eric Anholt <eric@anholt.net>
Fixes: 56c30bf17b ("tgsi: Saturate modifier obeys ExecMask. Implement NVIDIA [-1;+1] saturate mode.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10419>
(cherry picked from commit d1c0f62b42)
Instead of using num_textures, determine the texture count from the
last bit set in textures_used.
Fixes ADDR_RANGE_FAULTs when draw_textured_quad writes only stencil.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10422>
(cherry picked from commit c7076e03e5)
If no slices were valid (the resource is uninitialized), we were reading
a bogus PIPE_FORMAT_NONE format from the blit.dst.format. Fix this --
and guard against scope similar issues -- by hoisting the blit
assignments out of the loop so they're valid.
Fixes: 9d0ad7fd2e ("panfrost: Patch the gallium driver to use pan_image_layout_init()")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10415>
(cherry picked from commit c220976fd0)
Buffer copies with CP DMA aren't synced.
Fix dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.65536
flakes on GFX10+.
Fixes: e870796113 ("radv: prefer CP DMA for GTT buffer copies/clears on dGPUs due to slow PCIe")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10427>
(cherry picked from commit 3d979c9169)
The number of padded words is per IB, so it should be reset.
Found with Valgrind and dEQP-VK.api.command_buffers.record_many_draws*
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10376>
(cherry picked from commit f9e9b21e10)
Found with Valgrind and dEQP-VK.api.command_buffers.record_many_draws*.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10376>
(cherry picked from commit ec0d3701cd)
GFX6 has no CLEAR_STATE.
One step towards Vulkan conformance on these old chips.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10347>
(cherry picked from commit a12b844d40)
resetting a query pool+qbo dumpsters the existing qbo results,
so these need to be copied to the new qbo if they exist, and then the query
id needs to be updated to match the expected result offset so everything
keeps working as expected
Fixes: 00fc85a011 ("zink: reset queries when suspending if >50% of total pool is used")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10268>
(cherry picked from commit 79790e276f)
if the query has never been stopped, then doing an implicit reset here does
nothing except give the gpu more work
Fixes: 00fc85a011 ("zink: reset queries when suspending if >50% of total pool is used")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10268>
(cherry picked from commit 55b2b9b389)
I think at one point before staging resource flagging was less reliable
this method made sense, but now it's worse
Fixes: 6ff6d01c37 ("zink: don't use cached mem for staging resources")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10363>
(cherry picked from commit e34dc0840b)
this is broken after the backing object split because resources themselves
no longer have guaranteed lifetimes
Fixes: 616720d6ae ("zink: track resource_object usage instead of resource usage")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10270>
(cherry picked from commit de31a510cc)
always casting this to a u64 is invalid if the value is just a bool,
and it even generates ASAN/valgrind errors about uninitialized reads
Fixes: 41450b03a8 ("softpipe: implement conditional rendering")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10398>
(cherry picked from commit 8dbb022b8a)
Otherwise the dual-source input load is moved further down in the
shader, so the registers can get clobbered before then.
Fixes text not being visible in Alacritty.
Fixes: 52863f2e60 ("pan/bi: Enable all nir_opt_move/sink optimizations")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10089>
(cherry picked from commit ab3a72cc20)
The bug #4657 mixed up which commit was actually responsible for
the regression, so re-apply this patch.
The indirect draw call already encodes the index bias so that no
additional encoding in the hardware is needed in this case.
This fixes a regression with a number of tests from
dEQP-GLES31.functional.draw_indirect.random.*
Fixes: c6c532faa8
"gallium/u_vbuf: use updated pipe_draw_start_count while using draw_vbo"
Closes#4671
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10388>
(cherry picked from commit 0cae8d372e)
Normally, we never see NULL in a source. However, starting with
eab1c55590, we can with a SHADER_OPCODE_SEND if it only has the first
payload. We were inserting barriers which adds unnecessary scheduling
dependencies and takes a lot of compile time because inserting a single
barrier is an O(n) operation.
All the extra O(n) can have a surprisingly large effect. This cuts the
runtime of dEQP-VK.binding_model.buffer_device_address.set3.depth3.
basessbo.convertcheckuv2.store.single.std140.frag by a factor of 20x for
a debug build.
Shader-db results on ICL:
total instructions in shared programs: 19918983 -> 19921610 (0.01%)
instructions in affected programs: 884074 -> 886701 (0.30%)
helped: 1688
HURT: 817
helped stats (abs) min: 1 max: 163 x̄: 4.23 x̃: 1
helped stats (rel) min: 0.02% max: 12.50% x̄: 1.08% x̃: 0.61%
HURT stats (abs) min: 1 max: 2674 x̄: 11.95 x̃: 2
HURT stats (rel) min: 0.11% max: 70.22% x̄: 1.71% x̃: 1.03%
95% mean confidence interval for instructions value: -1.97 4.06
95% mean confidence interval for instructions %-change: -0.28% -0.06%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 976503324 -> 975884809 (-0.06%)
cycles in affected programs: 82581703 -> 81963188 (-0.75%)
helped: 4144
HURT: 5010
helped stats (abs) min: 1 max: 79294 x̄: 311.31 x̃: 8
helped stats (rel) min: <.01% max: 53.69% x̄: 2.00% x̃: 0.51%
HURT stats (abs) min: 1 max: 92266 x̄: 134.04 x̃: 8
HURT stats (rel) min: <.01% max: 218.09% x̄: 3.25% x̃: 0.53%
95% mean confidence interval for cycles value: -119.85 -15.29
95% mean confidence interval for cycles %-change: 0.68% 1.07%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).
total spills in shared programs: 10659 -> 12014 (12.71%)
spills in affected programs: 441 -> 1796 (307.26%)
helped: 7
HURT: 12
total fills in shared programs: 11551 -> 14429 (24.92%)
fills in affected programs: 993 -> 3871 (289.83%)
helped: 8
HURT: 11
total sends in shared programs: 1025832 -> 1025353 (-0.05%)
sends in affected programs: 2241 -> 1762 (-21.37%)
helped: 105
HURT: 1
helped stats (abs) min: 1 max: 87 x̄: 4.57 x̃: 2
helped stats (rel) min: 5.56% max: 54.72% x̄: 11.37% x̃: 10.00%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
95% mean confidence interval for sends value: -7.39 -1.65
95% mean confidence interval for sends %-change: -12.95% -7.70%
Sends are helped.
LOST: 93
GAINED: 109
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4648
Fixes: eab1c55590 "intel/fs: Support SENDS in SHADER_OPCODE_SEND"
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10412>
(cherry picked from commit 134af5ada2)
We need to bounds-check *before* we index the array, otherwise we peek
beyond the end of it.
Caught by Valgrind.
Fixes: dd29a7e5b0 ("zink: move descriptor barrier handling to main update function")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10367>
(cherry picked from commit a6a198da21)
On GFX6-7, the 8 and 16-bit integer add reductions use the 32-bit v_add
instruction, which clobbers the VCC register.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10346>
(cherry picked from commit 74c467d988)
I updated CTS and found
EQP-VK.renderpass.suballocation.multisample_resolve.b8g8r8a8_unorm.samples_4_resolve_level_*
was failing.
Fixes: b38879f8c5 ("vallium: initial import of the vulkan frontend")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10400>
(cherry picked from commit 32a2978949)
