For gl/cl interop, we can be importing things with array layout
(2d_array, etc), which need layer_size to be set correctly, matching
the exported resource.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40140>
Document nightly changes occuring in 6ea4fe98..c69f7904:
- KHR-GLES2.shaders.aggressive_optimizations.sin_vec3_frag,
crash, run out of the register space
- dEQP-GLES2.functional.shaders.indexing.matrix_subscript.mat4_static_loop_write_dynamic_loop_read_fragment,
passes now
- dEQP-GLES2.functional.color_clear.single_rgba,
new flake
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40142>
Add a new sc7180-trogdor-wormdingler-rev1-boe device type and move the
a618-vk job to it.
We'll have 12 boards, so we can increase parallelism and run fraction=1.
Update job settings and add one new expected fail, and skip a few
redundant tests in force-gmem mode.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39920>
The logic is supposed to find the stage with the maximum constlen to
trim for each time we have to trim a stage. But by not resetting
max_constlen each time, we would "trim" the same stage repeatedly,
leaving us thinking the total is below the limit when it actually isn't.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40127>
The HW uses ViewportIndex to select which GRAS_BIN_FOVEAT offset to use.
For normal 3d draws, either the ViewportIndex equals the view/layer or
we make the offset the same for all viewports/layers, but we aren't
aware of this in the 3d path and we always use viewport 0.
Use the HW offset 0 when subtracting the HW offset. This is a bit of a
hack, but it should work. This fixes LOAD_OP_LOAD with FDM.
Fixes: b34b089ca1 ("tu: Use GRAS bin offset registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39976>
Even when FDM isn't enabled, we can still emit patchpoints and duplicate
the viewport per-view or per-layer because the pipeline may include
VK_PIPELINE_CREATE_RENDERING_FRAGMENT_DENSITY_MAP_ATTACHMENT_BIT_EXT.
Before 25202d3e47 ("tu: Remove fdm argument from tu6_emit_tile_select")
we just silently skipped applying those patchpoints, but now we actually
apply them which means we need to re-emit viewport and scissor for
subsequent render passes.
Fixes: 25202d3e47 ("tu: Remove fdm argument from tu6_emit_tile_select")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39965>
We were inconsistently handling MESA_SHADER_KERNEL, which for the most
part should be treated identically to MESA_SHADER_COMPUTE.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40027>
Empirically, TCS outputs have to be aligned to 64 bytes,
otherwise stale data may be read in rare cases. The exact
reason is not clear, but tests and proprietary driver behavior
strongly point at the need for 64 byte alignment.
Fixes tesselation issues in at least "Conan Exiles" but likely in many
more cases.
CC: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39890>
If you were to try to reg allocate to more full regs than the file has,
you'll end up bit clearing off of available[]/available_to_evict[] and
corrupting the RB tree. Let's make sure we don't land there again.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39997>
As the comment says, we want to limit our pressure based on underlying HW
reg file size, not max it out to HW reg file size. This caused us to not
spill when we should when the HW reg size was bigger than the ISA reg file
size, leading to OOB writes in RA when it tried to allocate to the limit
pressure we spilled to.
Fixes segfaults in llama.cpp's test-backend-ops.
Fixes: e6e34883a9 ("ir3: Add wavesize control")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14846
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39997>
When these are correctly mapped to draw usage, we can't rely on them
being globally initialized in tu_init_hw(). They need to be re-
initialized after rp stomping.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39819>
Use information about register usage to decide what to dump for register
summaries. If --allregs, we continue to dump all regs that we have seen
a register write for. Otherwise we dump registers that are written
since last summary (as before) along with regs with the appropriate
usage.
A new column at the start of the line will show a '?' for registers that
don't match the existing usage (ie. they have been written but usage
doesn't match current "draw"). This could simply mean it is the first
"draw" in the render-pass (collecting per-renderpass values). Or it
could mean a mis-attributed or missing register usage. This new column
is only included for a6xx and newer, since older gens don't have usage
specified in xml.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14829
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39819>
We have other better tests for this now. And the next patch will
balloon the reference trace to 90MB due to large # of draw calls. So
just drop this test.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39819>
The existing implementation did not account for register names that
contain the suffix multiple times (ie. FOO_HIT_COUNT_HI).
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39819>
With TU_DEBUG=gmem,3d_load seen at least in: "Industria" and "NieR Replicant"
TU_DEBUG=noconcurrentresolves also prevent the issue.
We have to wait until all CP_EVENT_WRITE::BLIT are completed,
otherwise writing to depth image as color confuses HW.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39236>
Adjust or fill out various properties for the a830 GPU, setting up a gen1
base. So far these mostly mirror the gen2 properties, except for gmem
config layouts, and they will probably further diverge down the line.
A new GPU ID for a830 is also added, Turnip there runs on top of KGSL.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39874>
With a8xx a lot of chicken bit and other device-specific magic register
handling has moved into the kernel, which leaves a list of register writes
that could be more commonly shared between all a8xx devices.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39874>
lua_pushunsigned was introduced in Lua 5.2, deprecated in 5.3,
and removed in 5.4. Replace it with lua_pushinteger which has
been available since Lua 5.0 and handles the uint32_t value
safely via implicit widening to the 64-bit lua_Integer type.
This fixes the build with Lua 5.5:
../src/freedreno/decode/script.c: In function 'pushdecval':
../src/freedreno/decode/script.c:182:7: error: implicit declaration of function 'lua_pushunsigned'; did you mean 'lua_pushinteger'? [-Wimplicit-function-declaration]
182 | lua_pushunsigned(L, val.u);
| ^~~~~~~~~~~~~~~~
| lua_pushinteger
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39901>
