fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 09:38:07 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

freedreno/registers: Usage additions/corrections

Browse source 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39819>
This commit is contained in:
Rob Clark 2026-02-10 12:00:36 -08:00 • committed by Marge Bot
parent a99164651e
commit 48c2e15117
2 changed files with 24 additions and 23 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/freedreno/common/freedreno_devices.py
View file

@ -1145,7 +1145,7 @@ a740_raw_magic_regs = [
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_LRZ_CNTL2, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_A2D_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02080000],
[A6XXRegs.REG_A6XX_VPC_DBG_ECO_CNTL, 0x02000000],
[A6XXRegs.REG_A6XX_UCHE_UNKNOWN_0E12, 0],
@ -1251,7 +1251,7 @@ add_gpus([
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_LRZ_CNTL2, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_A2D_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02080000],
[A6XXRegs.REG_A6XX_VPC_DBG_ECO_CNTL, 0x02000000],
[A6XXRegs.REG_A6XX_UCHE_UNKNOWN_0E12, 0],
@ -1422,7 +1422,7 @@ add_gpus([
[A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0x00004800],
[A6XXRegs.REG_A7XX_RB_LRZ_CNTL2, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_A2D_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02082000],
[A6XXRegs.REG_A7XX_VPC_UNKNOWN_930A, 0],

41
src/freedreno/registers/adreno/a6xx.xml
View file

@ -2738,7 +2738,8 @@ by a particular renderpass/blit.
<reg32 offset="0x8813" name="RB_DEPTH_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/>
<reg32 offset="0x8814" name="RB_STENCIL_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/>
<reg32 offset="0x8815" name="RB_RESOLVE_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/>
<reg32 offset="0x8815" name="RB_RESOLVE_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-" usage="resolve"/>
<reg32 offset="0x88af" name="RB_RESOLVE_GMEM_PARTITION" variants="A8XX-" usage="resolve"/>
<array offset="0x8930" name="RB_MRT_GMEM_DIMENSION" variants="A8XX-" stride="1" length="8">
<reg32 offset="0" name="REG" type="a8xx_gmem_dimension"/>
@ -2807,7 +2808,7 @@ by a particular renderpass/blit.
<reg32 offset="0x8c2e" name="RB_A2D_CLEAR_COLOR_DW2" usage="blit"/>
<reg32 offset="0x8c2f" name="RB_A2D_CLEAR_COLOR_DW3" usage="blit"/>
<reg32 offset="0x8c34" name="RB_UNKNOWN_8C34" variants="A7XX-" usage="cmd"/>
<reg32 offset="0x8c34" name="RB_A2D_UNKNOWN_8C34" variants="A7XX-" usage="blit"/>
<!-- 0x8c35-0x8dff invalid -->
@ -3227,10 +3228,10 @@ by a particular renderpass/blit.
<reg32 offset="0x9b17" name="PC_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/>
<reg32 offset="0x9b18" name="PC_BV_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/>
<reg32 offset="0x930a" name="VPC_UNKNOWN_930A" variants="A7XX"/>
<reg32 offset="0x930a" name="VPC_UNKNOWN_930A" variants="A7XX" usage="draw"/>
<reg32 offset="0x9313" name="VPC_UNKNOWN_9313" variants="A8XX-"/>
<reg32 offset="0x9e17" name="PC_UNKNOWN_9E17" variants="A8XX-"/>
<reg32 offset="0x9313" name="VPC_UNKNOWN_9313" variants="A8XX-" usage="draw"/>
<reg32 offset="0x9e17" name="PC_UNKNOWN_9E17" variants="A8XX-" usage="draw"/>
<reg32 offset="0x960a" name="VPC_FLATSHADE_MODE_CNTL" variants="A7XX"/>
<reg32 offset="0x9741" name="VPC_FLATSHADE_MODE_CNTL" variants="A8XX-"/>
@ -4478,14 +4479,14 @@ by a particular renderpass/blit.
</reg32>
<reg32 offset="0xb2c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A7XX-" usage="blit"/>
<reg32 offset="0xb2c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A7XX-">
<reg32 offset="0xb2c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A7XX-" usage="blit">
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
</reg32>
<reg64 offset="0xb2c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A7XX" usage="blit"/>
<!-- gen8 can use an unaligned base for IMG_BUFFER: -->
<reg64 offset="0xb2c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" variants="A8XX-" usage="blit"/>
<reg32 offset="0xb2c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A7XX-">
<reg32 offset="0xb2c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A7XX-" usage="blit">
<!--
Bits from 3..9 must be zero unless 'TPL1_A2D_BLT_CNTL::TYPE'
is A6XX_TEX_IMG_BUFFER, which allows for lower alignment.
@ -4508,17 +4509,17 @@ by a particular renderpass/blit.
<reg64 offset="0xb2ca" name="TPL1_A2D_SRC_TEXTURE_FLAG_BASE" type="address" align="16" variants="A7XX-" usage="blit"/>
<reg32 offset="0xb2cc" name="TPL1_A2D_SRC_TEXTURE_FLAG_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="blit"/>
<reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/>
<reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/>
<reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX"/>
<reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX"/>
<reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX" usage="blit"/>
<reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX" usage="blit"/>
<reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX" usage="blit"/>
<reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX" usage="blit"/>
<reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A6XX" usage="cmd"/>
<reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX"/>
<reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/>
<reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/>
<reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/>
<reg32 offset="0xb2d1" name="TPL1_A2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-"/>
<reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX" usage="blit"/>
<reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX" usage="blit"/>
<reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX" usage="blit"/>
<reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX" usage="blit"/>
<reg32 offset="0xb2d1" name="TPL1_A2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="cmd"/>
<bitset name="a7xx_tpl1_a2d_blt_cntl" inline="yes">
<bitfield name="RAW_COPY" pos="0" type="boolean"/>
<bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/>
@ -4642,7 +4643,7 @@ by a particular renderpass/blit.
</bitset>
<reg32 offset="0xb980" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A6XX" usage="draw"/>
<reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob -->
<reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX" usage="draw"/> <!-- never used by blob -->
<reg32 offset="0xb982" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A6XX" usage="draw">
<!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the
A3xx field, except that it's not necessary to set it to anything but the maximum, since
@ -4909,13 +4910,13 @@ by a particular renderpass/blit.
</reg32>
<reg32 offset="0xa9c0" name="SP_CS_BINDLESS_INVALIDATE" usage="compute"/>
<reg32 offset="0xab08" name="SP_GFX_BINDLESS_INVALIDATE"/>
<reg32 offset="0xab08" name="SP_GFX_BINDLESS_INVALIDATE" usage="draw"/>
<reg32 offset="0xbb10" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="draw"/>
<reg32 offset="0xab03" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="draw"/>
<array offset="0xab40" name="SP_SHARED_CONSTANT_GFX" stride="1" length="64" variants="A7XX"/>
<array offset="0xab30" name="SP_SHARED_CONSTANT_GFX" stride="1" length="128" variants="A8XX-"/>
<array offset="0xab40" name="SP_SHARED_CONSTANT_GFX" stride="1" length="64" variants="A7XX" usage="draw"/>
<array offset="0xab30" name="SP_SHARED_CONSTANT_GFX" stride="1" length="128" variants="A8XX-" usage="draw"/>
<reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd,compute">
<doc>