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freedreno+ir3: Implement CL isam mode

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CL expected different coord rounding, etc.  Switch based on shader type.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40027>
This commit is contained in:
Rob Clark 2026-02-19 09:28:44 -08:00 • committed by Marge Bot
parent ac7b457927
commit 005ce4057c
3 changed files with 38 additions and 18 deletions
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6
src/freedreno/ir3/ir3_nir.c
View file

@ -763,7 +763,11 @@ ir3_finalize_nir(struct ir3_compiler *compiler,
NIR_PASS(_, s, ir3_nir_lower_sparse_residency);
NIR_PASS(_, s, ir3_nir_min_lod_workaround);
if (compiler->array_index_add_half)
/* for opencl kernels, TPL1_MODE_CNTL should be configured for
* isammode=CL and .arraycoordroundmode = ROUND_NEAREST_EVEN,
* as opposed to gl/vk compute shaders which follow GL rules:
*/
if (compiler->array_index_add_half && (s->info.stage != MESA_SHADER_KERNEL))
OPT(s, ir3_nir_lower_array_sampler);
OPT(s, ir3_nir_lower_image_processing);

15
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -949,13 +949,6 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs)
crb.add(A6XX_SP_UNKNOWN_A9A8());
crb.add(A6XX_SP_MODE_CNTL(
.constant_demotion_enable = true,
.isammode = ISAMMODE_GL,
.shared_consts_enable = false,
)
);
crb.add(A6XX_VFD_MODE_CNTL(.vertex = true, .instance = true));
if (CHIP == A6XX)
crb.add(VPC_UNKNOWN_9107(CHIP));
@ -996,14 +989,6 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs)
crb.add(VPC_UNKNOWN_9210(CHIP));
}
crb.add(TPL1_MODE_CNTL(CHIP,
.isammode = ISAMMODE_GL,
.texcoordroundmode = COORD_TRUNCATE,
.nearestmipsnap = CLAMP_ROUND_TRUNCATE,
.destdatatypeoverride = true,
.clamp_disable = true,
));
crb.add(SP_REG_PROG_ID_3(
CHIP,
.linelengthregid = INVALID_REG,

35
src/gallium/drivers/freedreno/a6xx/fd6_program.cc
View file

@ -45,11 +45,42 @@ template <chip CHIP>
static void
emit_shader_regs(struct fd_context *ctx, fd_cs &cs, const struct ir3_shader_variant *so)
{
fd_crb crb(cs, 12);
fd_crb crb(cs, 14);
mesa_shader_stage type = so->type;
if (type == MESA_SHADER_KERNEL)
enum a6xx_isam_mode isam_mode = ISAMMODE_GL;
if (type == MESA_SHADER_KERNEL) {
isam_mode = ISAMMODE_CL;
type = MESA_SHADER_COMPUTE;
}
crb.add(A6XX_SP_MODE_CNTL(
.constant_demotion_enable = true,
.isammode = isam_mode,
.shared_consts_enable = false,
));
if (isam_mode == ISAMMODE_GL) {
crb.add(TPL1_MODE_CNTL(CHIP,
.isammode = ISAMMODE_GL,
.texcoordroundmode = COORD_TRUNCATE,
.arraycoordroundmode = COORD_TRUNCATE,
.nearestmipsnap = CLAMP_ROUND_TRUNCATE,
.destdatatypeoverride = true,
.clamp_disable = true,
));
} else {
assert(isam_mode == ISAMMODE_CL);
crb.add(TPL1_MODE_CNTL(CHIP,
.isammode = ISAMMODE_CL,
.texcoordroundmode = COORD_TRUNCATE,
.arraycoordroundmode = COORD_ROUND_NEAREST_EVEN,
.nearestmipsnap = ROUND_CLAMP_TRUNCATE,
.destdatatypeoverride = false,
.clamp_disable = false,
));
}
enum a6xx_threadsize thrsz =
so->info.double_threadsize ? THREAD128 : THREAD64;