Passes all of `dEQP-EGL.functional.swap_buffers_with_damage.*`:
Passed: 36/54 (66.7%)
Failed: 0/54 (0.0%)
Not supported: 18/54 (33.3%)
Warnings: 0/54 (0.0%)
Waived: 0/54 (0.0%)
The "not supported" ones are the `preserve_buffer_*` tests, which is not
supported on X11/DRI3.
Cc: 20.2 <mesa-stable>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3030
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6132>
(cherry picked from commit 326eb56718)
When calling glWaitSync (fence_server_sync), we added dependencies
in all batches (render and compute) on existing work. Even if
applications don't use compute at all, they theoretically could,
so we record that the compute batch depends on the render batch.
But if the application truly doesn't use compute, or rarely uses
it, we ended up recording dependencies on _all_ previous render
batches, racking up a massive list of syncobjs. Not only is this
pointless, it also meant that we never allowed the kernel to free
the underlying i915_request objects.
There are a number of solutions to this problem, but for now, we
take a simple one: when recording a new syncobj dependency, we
walk the list and see if any of them have already passed. If so,
that dependency has been fulfilled. We no longer need to track it,
and can simply drop it from the list, unreferencing the syncobj.
Android's SurfaceFlinger in particular was hitting this issue,
as it uses glWaitSync, doesn't typically use compute shaders,
and runs for long durations.
Thanks to Yang A Shi <yang.a.shi@intel.com> and
Kefei Yao <kefei.yao@intel.com> for their excellent work in
tracking down this issue!
Fixes: f459c56be6 ("iris: Add fence support using drm_syncobj")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Yang A Shi <yang.a.shi@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6463>
(cherry picked from commit 6b1a56b908)
Swapping the order of the loops makes the logic much easier to follow:
for each point in our fence, if it hasn't gone by, make future work in
all batches depend on it. Both loops are necessary, and now it's
clearer why.
(This doesn't actually fix a bug but needs to be cherry-picked for
the next patch to apply, which does fix a bug.)
Fixes: f459c56be6 ("iris: Add fence support using drm_syncobj")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Yang A Shi <yang.a.shi@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6463>
(cherry picked from commit e98c7a6634)
This would move the old exec mask back into exec. This also fixes the
live_out_exec.
Issue found in dEQP-VK.graphicsfuzz.cosh-return-inf-unused
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: 20.2 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6212>
(cherry picked from commit a537c9e73f)
The content of rsc->pending_ctx could be changed from multiple contexts
and thus from multiple threads. The per-context lock is not sufficient
to protect this list. Add per-resource lock to protect this list.
Fixes: e5cc66dfad ("etnaviv: Rework locking")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6454>
(cherry picked from commit 60975ebe58)
This function is not used, remove it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6454>
(cherry picked from commit da660c90bf)
PTB assumes that base instance to be 0 at start of tile, but hw would
not do that, we need to set it. It is worth to note that the opcode
name is somewhat confusing as what it really sets is the base
instance. We could rename the opcode, but then the name would be
different to the original Broadcom name, so confusing in any case.
This fixes several dEQP-GLES3 and dEQP-GLES31 tests that passes
individually, but started to fail depending on other tests running
before using base instance different to zero.
This is the backport of a Vulkan patch that fixed some Vulkan CTS
tests that start to fails after some other tests used an instance id.
CC: 20.2 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6447>
(cherry picked from commit 05a0349949)
Return the actual number of planes in these formats (one) instead of the
number of planes used for lowering (two).
Fixes: d5c857837a ("gallium/dri2: Fix creation of multi-planar modifier images")
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6449>
(cherry picked from commit 36bd3e9868)
Fixes: 138c003d22 ("meson: deprecated 'true' and 'false' in combo options for 'enabled' and 'disabled'")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6397>
(cherry picked from commit 855afe0144)
If you have a sequence where there is a single buffer associated with
the current render target, and then you end up shadowing it on the 3d
pipe (u_blitter), because of how we swap the new shadow and rsc before
the back-blit, you could end up confusing things into thinking that
the blitters framebuffer state is the same as the current framebuffer
state.
Re-organizing the sequence to swap after the blit is complicated when
also having to deal with CPU memcpy blit path, and the batch/rsc
accounting. So instead just detect this case and flush if we need to.
Fixes:
dEQP-GLES31.functional.stencil_texturing.render.depth24_stencil8_clear
dEQP-GLES31.functional.stencil_texturing.render.depth24_stencil8_draw
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6434>
(cherry picked from commit 1fa43a4a8e)
writeSpirv() already takes care of that, and calling it twice seems to
duplicate functions and cause problems when processing execution modes.
Fixes: 2043c5f37c "clover/llvm: Add functions for compiling from..."
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6306>
(cherry picked from commit e3e45e2456)
We were using the wrong conversion opcode. The high bits are also not
zero'd on GFX10, which can cause v_cvt_pk_u16_u32 to clamp.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: df645fa369 ('aco: implement VK_KHR_shader_float_controls')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6346>
(cherry picked from commit 9c1e0d86a8)
Section 5.11 (Out-of-Bounds Accesses) of the GLSL 4.60 spec says:
"In the subsections described above for array, vector, matrix and
structure accesses, any out-of-bounds access produced undefined
behavior.... Out-of-bounds writes may be discarded or overwrite
other variables of the active program."
Fixes crashes when dereferencing gl_ClipDistance and gl_TessLevel*, e.g:
int index = -1;
gl_ClipDistance[index] = -1;
When LowerCombinedClipCullDistance is true.
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6363>
(cherry picked from commit e802bff69e)
On glmark2-es2 -bterrain:
594.05KB leaked over 9282 calls from:
panfrost_batch_update_bo_access
at ../src/gallium/drivers/panfrost/pan_job.c:462
in /home/alyssa/rockchip_dri.so
panfrost_batch_add_bo
at ../src/gallium/drivers/panfrost/pan_job.c:560
panfrost_batch_add_bo
at ../src/gallium/drivers/panfrost/pan_job.c:519
in /home/alyssa/rockchip_dri.so
panfrost_batch_add_resource_bos
at ../src/gallium/drivers/panfrost/pan_job.c:569
panfrost_batch_add_fbo_bos
at ../src/gallium/drivers/panfrost/pan_job.c:588
in /home/alyssa/rockchip_dri.so
panfrost_create_batch
at ../src/gallium/drivers/panfrost/pan_job.c:126
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: mesa-stable
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6373>
(cherry picked from commit 1cb47f8eea)
8.74KB leaked over 52 calls from:
0xffffbb5b9fc3
in ??
_mesa_hash_table_init
at ../src/util/hash_table.c:163
in /home/alyssa/rockchip_dri.so
_mesa_hash_table_create
at ../src/util/hash_table.c:186
_mesa_hash_table_u64_create
at ../src/util/hash_table.c:701
in /home/alyssa/rockchip_dri.so
panfrost_nir_assign_sysvals
at ../src/panfrost/util/pan_sysval.c:130
in /home/alyssa/rockchip_dri.so
midgard_compile_shader_nir
at ../src/panfrost/midgard/midgard_compile.c:2905
in /home/alyssa/rockchip_dri.so
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: mesa-stable
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6373>
(cherry picked from commit 680fb05f99)
Before we drop the reference.
160 calls with 0B peak consumption from:
0xffffbd9d2fc3
in ??
pan_compute_liveness
at ../src/panfrost/util/pan_liveness.c:127
in /home/alyssa/rockchip_dri.so
mir_compute_liveness
at ../src/panfrost/midgard/midgard_liveness.c:55
in /home/alyssa/rockchip_dri.so
midgard_opt_dead_code_eliminate
at ../src/panfrost/midgard/midgard_opt_dce.c:118
in /home/alyssa/rockchip_dri.so
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: mesa-stable
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6373>
(cherry picked from commit 8dd38e5a3e)
No need to put it on the context, we can keep it local in mir_squeeze
and drop when we're done.
15.77KB leaked over 85 calls from:
0xffffaed3bfc3
in ??
_mesa_hash_table_rehash
at ../src/util/hash_table.c:368
in /home/alyssa/rockchip_dri.so
hash_table_insert
at ../src/util/hash_table.c:403
in /home/alyssa/rockchip_dri.so
find_or_allocate_temp
at ../src/panfrost/midgard/mir_squeeze.c:48
in /home/alyssa/rockchip_dri.so
find_or_allocate_temp
at ../src/panfrost/midgard/mir_squeeze.c:35
in /home/alyssa/rockchip_dri.so
mir_squeeze_index
at ../src/panfrost/midgard/mir_squeeze.c:76
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: mesa-stable
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6373>
(cherry picked from commit 62637a913a)
After we compile from NIR to a native binary, we can throw away the NIR.
17.47KB leaked over 104 calls from:
0xffff87dcafc3
in ??
_mesa_hash_table_init
at ../src/util/hash_table.c:163
in /home/alyssa/rockchip_dri.so
_mesa_hash_table_create
at ../src/util/hash_table.c:186
nir_lower_vars_to_ssa_impl
at ../src/compiler/nir/nir_lower_vars_to_ssa.c:717
in /home/alyssa/rockchip_dri.so
nir_lower_vars_to_ssa
at ../src/compiler/nir/nir_lower_vars_to_ssa.c:817
optimise_nir
at ../src/panfrost/midgard/midgard_compile.c:504
in /home/alyssa/rockchip_dri.so
midgard_compile_shader_nir
at ../src/panfrost/midgard/midgard_compile.c:2895
in /home/alyssa/rockchip_dri.so
panfrost_build_blit_shader
at ../src/panfrost/lib/pan_blit.c:103
in /home/alyssa/rockchip_dri.so
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: mesa-stable
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6373>
(cherry picked from commit da6d0e3fac)
Fixes heaptrack leak:
19.37KB leaked over 63 calls from:
0xffff92bbefc3
in ??
nir_alu_instr_create
at ../src/compiler/nir/nir.c:442
in /home/alyssa/rockchip_dri.so
clone_alu
at ../src/compiler/nir/nir_clone.c:277
in /home/alyssa/rockchip_dri.so
clone_instr
at ../src/compiler/nir/nir_clone.c:495
in /home/alyssa/rockchip_dri.so
clone_block
at ../src/compiler/nir/nir_clone.c:544
clone_cf_list
at ../src/compiler/nir/nir_clone.c:594
clone_function_impl
at ../src/compiler/nir/nir_clone.c:672
in /home/alyssa/rockchip_dri.so
nir_shader_clone
at ../src/compiler/nir/nir_clone.c:744
in /home/alyssa/rockchip_dri.so
panfrost_shader_compile
at ../src/gallium/drivers/panfrost/pan_assemble.c:154
in /home/alyssa/rockchip_dri.so
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: mesa-stable
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6373>
(cherry picked from commit 9146f596ed)
The *2 here would bump into the *2 in regset, causing assertion failures
dumping CS programs. Just set the mergedregs flag on a6xx, and don't
duplicate the mergedregs logic. If you're dealing with new HW where we
don't know if mergedregs is set, you may need to tweak the flag during
disasm setup for the stats to make sense.
Fixes: f7bd3456d7 ("freedreno: deduplicate a3xx+ disasm")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6323>
(cherry picked from commit a27823ef2c)
During build on Android 10, build error occurred:
'''
[ 26% 456/1718] Gen Header: libfreedreno_registers_32 <= a3xx.xml.h
FAILED: out/target/product/pinephone/gen/STATIC_LIBRARIES/libfreedreno_registers_intermediates/registers/adreno/a3xx.xml.h
/bin/bash -c "PATH=/usr/bin:\$PATH python3 external/mesa3d/src/freedreno/registers/gen_header.py external/mesa3d/src/freedreno/registers/adreno/a3xx.xml > out/target/product/pinephone/gen/STATIC_LIBRARIES/libfreedreno_registers_intermediates/registers/adreno/a3xx.xml.h"
Traceback (most recent call last):
File "external/mesa3d/src/freedreno/registers/gen_header.py", line 470, in <module>
main()
File "external/mesa3d/src/freedreno/registers/gen_header.py", line 446, in main
xml_file = sys.argv[2]
IndexError: list index out of range
'''
Align build rules with meson fixes it.
Fixes: 62ebd342 ("freedreno/registers: split header build into subdirs")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6170>
(cherry picked from commit 8626d4cbef)
We really need to update the enum for consistency, but that involves
a bunch of GL & bitfield work which is error-prone, so since this is
a fix for stable lets do the simple things.
Confirmed that nothing in radv/aco/nir/spirv uses MAX_VERT_ATTRIB
except the one thing I bumped.
CC: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6120>
(cherry picked from commit f038b3a136)
