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panfrost: Free hash_to_temp map

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No need to put it on the context, we can keep it local in mir_squeeze
and drop when we're done.

15.77KB leaked over 85 calls from:
    0xffffaed3bfc3
      in ??
    _mesa_hash_table_rehash
      at ../src/util/hash_table.c:368
      in /home/alyssa/rockchip_dri.so
    hash_table_insert
      at ../src/util/hash_table.c:403
      in /home/alyssa/rockchip_dri.so
    find_or_allocate_temp
      at ../src/panfrost/midgard/mir_squeeze.c:48
      in /home/alyssa/rockchip_dri.so
    find_or_allocate_temp
      at ../src/panfrost/midgard/mir_squeeze.c:35
      in /home/alyssa/rockchip_dri.so
    mir_squeeze_index
      at ../src/panfrost/midgard/mir_squeeze.c:76

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: mesa-stable
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6373>
This commit is contained in:
Alyssa Rosenzweig 2020-08-18 08:23:13 -04:00 • committed by Tomeu Vizoso
parent da6d0e3fac
commit 62637a913a
3 changed files with 13 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/panfrost/midgard/compiler.h
View file

@ -293,8 +293,6 @@ typedef struct compiler_context {
/* Constants which have been loaded, for later inlining */
struct hash_table_u64 *ssa_constants;
/* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
struct hash_table_u64 *hash_to_temp;
int temp_count;
int max_hash;

1
src/panfrost/midgard/midgard_compile.c
View file

@ -2855,7 +2855,6 @@ midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_b
/* Initialize at a global (not block) level hash tables */
ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
/* Lower gl_Position pre-optimisation, but after lowering vars to ssa
* (so we don't accidentally duplicate the epilogue since mesa/st has

23
src/panfrost/midgard/mir_squeeze.c
View file

@ -30,13 +30,14 @@
* as such */
static unsigned
find_or_allocate_temp(compiler_context *ctx, unsigned hash)
find_or_allocate_temp(compiler_context *ctx, struct hash_table_u64 *map,
unsigned hash)
{
if (hash >= SSA_FIXED_MINIMUM)
return hash;
unsigned temp = (uintptr_t) _mesa_hash_table_u64_search(
ctx->hash_to_temp, hash + 1);
map, hash + 1);
if (temp)
return temp - 1;
@ -45,7 +46,7 @@ find_or_allocate_temp(compiler_context *ctx, unsigned hash)
temp = ctx->temp_count++;
ctx->max_hash = MAX2(ctx->max_hash, hash);
_mesa_hash_table_u64_insert(ctx->hash_to_temp,
_mesa_hash_table_u64_insert(map,
hash + 1, (void *) ((uintptr_t) temp + 1));
return temp;
@ -57,10 +58,10 @@ find_or_allocate_temp(compiler_context *ctx, unsigned hash)
void
mir_squeeze_index(compiler_context *ctx)
{
struct hash_table_u64 *map = _mesa_hash_table_u64_create(NULL);
/* Reset */
ctx->temp_count = 0;
/* TODO don't leak old hash_to_temp */
ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
/* We need to prioritize texture registers on older GPUs so we don't
* fail RA trying to assign to work registers r0/r1 when a work
@ -68,17 +69,19 @@ mir_squeeze_index(compiler_context *ctx)
mir_foreach_instr_global(ctx, ins) {
if (ins->type == TAG_TEXTURE_4)
ins->dest = find_or_allocate_temp(ctx, ins->dest);
ins->dest = find_or_allocate_temp(ctx, map, ins->dest);
}
mir_foreach_instr_global(ctx, ins) {
if (ins->type != TAG_TEXTURE_4)
ins->dest = find_or_allocate_temp(ctx, ins->dest);
ins->dest = find_or_allocate_temp(ctx, map, ins->dest);
for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i)
ins->src[i] = find_or_allocate_temp(ctx, ins->src[i]);
ins->src[i] = find_or_allocate_temp(ctx, map, ins->src[i]);
}
ctx->blend_input = find_or_allocate_temp(ctx, ctx->blend_input);
ctx->blend_src1 = find_or_allocate_temp(ctx, ctx->blend_src1);
ctx->blend_input = find_or_allocate_temp(ctx, map, ctx->blend_input);
ctx->blend_src1 = find_or_allocate_temp(ctx, map, ctx->blend_src1);
_mesa_hash_table_u64_destroy(map, NULL);
}