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Author SHA1 Message Date
Emma Anholt
10ba7675c8 nir/uub: Use an optional max_samples from drivers for sample counts. 
This triggers some unrolling in Fallout 4, GTAV, and Rocky Planet in my
shader-db.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38585>
 2025-12-11 14:26:11 +00:00
Samuel Pitoiset
a89118c5b0 radv: fix race condition when getting the blit queue
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Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14439
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38883>
 2025-12-11 11:16:29 +00:00
Samuel Pitoiset
31a24caad9 radv: only include executable size when capturing shaders with RGP 
This might help RGP to not try to disassemble past s_endpgm and crashes
on unknown instructions.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14419
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38885>
 2025-12-11 10:56:10 +00:00
Georg Lehmann
ef246aaf72 aco/isel: emit register copies for workgroup ids 
This way, we don't overestimate SGPR pressure.

Foz-DB Navi48:
Totals from 1413 (1.45% of 97637) affected shaders:
Instrs: 3468375 -> 3468585 (+0.01%); split: -0.01%, +0.02%
CodeSize: 18643064 -> 18643520 (+0.00%); split: -0.01%, +0.01%
VGPRs: 71776 -> 71788 (+0.02%)
SpillSGPRs: 18575 -> 18561 (-0.08%)
Latency: 23207643 -> 23207998 (+0.00%); split: -0.00%, +0.01%
InvThroughput: 8116806 -> 8116541 (-0.00%); split: -0.01%, +0.00%
VClause: 75250 -> 75252 (+0.00%); split: -0.00%, +0.00%
SClause: 65274 -> 65283 (+0.01%); split: -0.02%, +0.04%
Copies: 275750 -> 275942 (+0.07%); split: -0.03%, +0.10%
PreSGPRs: 70246 -> 69072 (-1.67%)
VALU: 1892111 -> 1892092 (-0.00%); split: -0.00%, +0.00%
SALU: 523460 -> 523648 (+0.04%); split: -0.02%, +0.05%
VOPD: 41097 -> 41102 (+0.01%)

Sadly the RA noise is slightly negative for instruction count.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38830>
 2025-12-11 08:06:59 +00:00
Georg Lehmann
839a035564 aco/optimizer: propagate fixed regs to copy/extract/insert 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38830>
 2025-12-11 08:06:58 +00:00
Georg Lehmann
d32dd5e1df aco/optimizer: propagate fixed registers 
Foz-DB Navi48:
Totals from 351 (0.36% of 97637) affected shaders:
Instrs: 3568192 -> 3567166 (-0.03%)
CodeSize: 18890368 -> 18886304 (-0.02%)
Latency: 17047945 -> 17048185 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 3185739 -> 3185813 (+0.00%); split: -0.00%, +0.00%
SClause: 61544 -> 61536 (-0.01%)
Copies: 271592 -> 270845 (-0.28%)
PreSGPRs: 17186 -> 17094 (-0.54%)
PreVGPRs: 21897 -> 21901 (+0.02%)
VALU: 2003976 -> 2003980 (+0.00%)
SALU: 468403 -> 467664 (-0.16%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38830>
 2025-12-11 08:06:58 +00:00
Georg Lehmann
b798ace443 aco/optimizer: fix skip_smem_offset_align with non temp register operands 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38830>
 2025-12-11 08:06:58 +00:00
Georg Lehmann
911e1ce168 aco/isel: emit exec copy for ballot(true) 
Once copy propagated in the optimizer, this will allow
using nir_opt_uniform_subgroup without too many regressions.

Foz-DB Navi48:
Totals from 405 (0.41% of 97637) affected shaders:
Instrs: 3796716 -> 3796894 (+0.00%); split: -0.00%, +0.00%
CodeSize: 20116136 -> 20116652 (+0.00%); split: -0.00%, +0.00%
Latency: 18326661 -> 18327114 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 3353206 -> 3353268 (+0.00%); split: -0.00%, +0.00%
Copies: 292307 -> 293830 (+0.52%)
SALU: 507523 -> 507738 (+0.04%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38830>
 2025-12-11 08:06:58 +00:00
Georg Lehmann
72e3071751 aco/optimizer: keep pass_flags valid for all instructions 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38830>
 2025-12-11 08:06:57 +00:00
Marek Olšák
308da55f1a radv,radeonsi: use FRAG_RESULT_DUAL_SRC_BLEND 
this is slightly nicer

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38604>
 2025-12-10 19:16:46 +00:00
Yonggang Luo
be4ad5c819 meson: Remove VK_ICD_FILENAMES totally from source tree. 
This is a follow up of
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28516

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@google.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> hk changes
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> for RADV changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38637>
 2025-12-10 14:46:11 +00:00
Valentine Burley
4cbf5062b7 ci: Uprev GL & GLES CTS 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38071>
 2025-12-10 11:31:33 +00:00
Georg Lehmann
bb58ba2075 aco/optimizer: propagate salu fabs
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Foz-DB Navi48:
Totals from 5156 (5.28% of 97637) affected shaders:
Instrs: 12713219 -> 12694317 (-0.15%); split: -0.15%, +0.00%
CodeSize: 67099236 -> 67037588 (-0.09%); split: -0.13%, +0.04%
VGPRs: 352620 -> 352608 (-0.00%)
SpillSGPRs: 22032 -> 22031 (-0.00%)
Latency: 68288972 -> 68271858 (-0.03%); split: -0.03%, +0.00%
InvThroughput: 13639078 -> 13633997 (-0.04%); split: -0.04%, +0.00%
VClause: 235194 -> 235186 (-0.00%); split: -0.01%, +0.00%
SClause: 249057 -> 249012 (-0.02%); split: -0.03%, +0.01%
Copies: 963813 -> 960529 (-0.34%); split: -0.36%, +0.02%
Branches: 321041 -> 321039 (-0.00%)
PreSGPRs: 303392 -> 303295 (-0.03%); split: -0.03%, +0.00%
VALU: 7134563 -> 7134533 (-0.00%); split: -0.00%, +0.00%
SALU: 1913802 -> 1899948 (-0.72%); split: -0.72%, +0.00%
VOPD: 19914 -> 19885 (-0.15%); split: +0.01%, -0.15%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38723>
 2025-12-10 10:07:12 +00:00
Georg Lehmann
04037c7af3 aco/optimizer: propagate salu fneg 
Foz-DB Navi48:
Totals from 23796 (24.37% of 97637) affected shaders:
MaxWaves: 638922 -> 638898 (-0.00%)
Instrs: 32968990 -> 32880147 (-0.27%); split: -0.28%, +0.01%
CodeSize: 174252352 -> 173922400 (-0.19%); split: -0.20%, +0.01%
VGPRs: 1396472 -> 1396592 (+0.01%)
SpillSGPRs: 63672 -> 63599 (-0.11%)
Latency: 201025393 -> 200966204 (-0.03%); split: -0.05%, +0.02%
InvThroughput: 37429702 -> 37411026 (-0.05%); split: -0.06%, +0.01%
VClause: 534241 -> 534115 (-0.02%); split: -0.05%, +0.02%
SClause: 831765 -> 831559 (-0.02%); split: -0.07%, +0.05%
Copies: 2404134 -> 2400539 (-0.15%); split: -0.29%, +0.14%
Branches: 728518 -> 728503 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 1337403 -> 1336846 (-0.04%); split: -0.04%, +0.00%
PreVGPRs: 1017490 -> 1017521 (+0.00%); split: -0.00%, +0.00%
VALU: 18319620 -> 18318960 (-0.00%); split: -0.01%, +0.00%
SALU: 5069557 -> 5001384 (-1.34%); split: -1.38%, +0.03%
VOPD: 80235 -> 80172 (-0.08%); split: +0.13%, -0.21%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38723>
 2025-12-10 10:07:12 +00:00
Georg Lehmann
8b1340a52c aco/optimizer: validate uses
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Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38724>
 2025-12-10 09:40:13 +00:00
Georg Lehmann
ad3add311c aco/optimizer: fix uses in to_uniform_bool_instr 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38724>
 2025-12-10 09:40:13 +00:00
Marek Olšák
0c400fbed9 nir: give nir_lower_clip_cull_distance_array_vars a better name 
also rename the file

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38465>
 2025-12-10 05:16:34 +00:00
Marek Olšák
74995eb64d nir: split gathering array sizes from nir_lower_clip_cull_distance_array_vars 
nir_lower_clip_cull_distance_array_vars was sneakily updating
shader_info::clip/cull_distance_array_size.

This moves the gathering into a new function
nir_gather_clip_cull_distance_sizes_from_vars.

v2: remove assertions that prevented nir_lower_clip_cull_distance_array_vars
    from being used with non-compact arrays

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38465>
 2025-12-10 05:16:34 +00:00
Benjamin Cheng
72b43c0595 radv/video: Always end ref pic modification list
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The app-provided arrays should always end with IDC_END, but when
overriding we need to end the list with IDC_END as well.

Fixes: 2e21eec921 ("radv/video: Fix num_ref_idx_l{0,1} related overrides")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14436
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38858>
 2025-12-09 16:04:52 +00:00
Natalie Vock
6d799ac283 aco: Add pass for spilling call-related registers 
This is a post-RA pass that tracks registers that are preserved by the
ABI, but clobbered by shader code. The pass inserts scratch spills and
reloads in appropriate locations to ensure the register values at the
end of the shader are the same as they were at the start.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:55 +00:00
Natalie Vock
93a5919cee aco/util: Add aco::unordered_set 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:55 +00:00
Natalie Vock
0cfabe0613 aco/lower_to_hw_instr: Add scratch size in call lowering 
We did this in the preserved spiller previously, but let's move it here.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:55 +00:00
Natalie Vock
7059068b61 aco/spill: Restore registers spilled by call immediately 
Makes for better latency hiding if we're not short on registers
otherwise.

On top of RT function calls:
Totals from 7 (0.01% of 81072) affected shaders:

Instrs: 9084 -> 8980 (-1.14%)
CodeSize: 52564 -> 51976 (-1.12%)
SpillSGPRs: 244 -> 248 (+1.64%); split: -3.28%, +4.92%
SpillVGPRs: 360 -> 367 (+1.94%)
Latency: 138989 -> 135669 (-2.39%); split: -2.49%, +0.10%
InvThroughput: 35120 -> 35301 (+0.52%); split: -0.06%, +0.57%
VClause: 258 -> 241 (-6.59%)
SClause: 116 -> 117 (+0.86%)
Copies: 1290 -> 1311 (+1.63%)
Branches: 131 -> 119 (-9.16%)
VALU: 6125 -> 6143 (+0.29%); split: -0.20%, +0.49%
SALU: 920 -> 913 (-0.76%); split: -0.98%, +0.22%
VMEM: 1026 -> 989 (-3.61%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:55 +00:00
Natalie Vock
6616f25e43 aco/spill: Create linear VGPRs for spilling ABI-preserved SGPRs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:55 +00:00
Natalie Vock
6b2e766617 aco/ra: Handle linear VGPRs allocated by p_startpgm 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:54 +00:00
Natalie Vock
761efe9163 aco/spill: Reset scratch_rsrc on calls 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:54 +00:00
Natalie Vock
369a3c0dca aco/spill: Handle calls 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:54 +00:00
Natalie Vock
ecc548cd37 aco: Record required call spills during live-var analysis 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:53 +00:00
Natalie Vock
8bc5fdef53 aco: Remove unused p_reload_preserved def 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38281>
 2025-12-08 19:12:52 +00:00
Natalie Vock
8b7ad622ee aco/live_var_analysis: Count linear VGPRs as always preserved by calls 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37907>
 2025-12-08 18:50:31 +00:00
Natalie Vock
f692ac76ca radv/rt: Use traversal vars for object origin/direction in ahit/isec
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We already did the work of transforming the ray data, no need to do it
multiple times.

Should theoretically be a lot better. However, none of the fossils
appear to use object-space ray data in anyhit/intersection shaders. :(

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38809>
 2025-12-08 18:29:49 +00:00
Natalie Vock
a488203e85 radv/rt: Refactor and split radv_nir_rt_shader.c 
This splits up radv_nir_rt_shader.c into several parts.
The first part is all ray traversal lowering for RT pipelines, located
at radv_nir_rt_traversal_shader.c. It implements building the traversal
loop, including inlined any-hit/intersection shaders (optionally as a
completely separate shader).

The second part is lowering for individual RT stages (right now,
monolithic vs. CPS-style separate compilation). Each lowering technique
lives in its own file (radv_nir_rt_stage_{monolithic,cps}.c).

Code shared between RT lowering techniques (shader inlining helpers and
storage lowering passes) gets moved into radv_nir_rt_stage_common.c.

One header, radv_nir_rt_stage.h, is the public interface for RT pipeline
stage lowering. Functions exposed to users (really just
radv_pipeline_rt.c) go there. The header for internal shared helpers is
radv_nir_rt_stage_common.c.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38809>
 2025-12-08 18:29:49 +00:00
Arcady Goldmints-Orlov
0df8aa940c nir: Use nir_shader_intrinsics_pass in nir_lower_io_to_scalar
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Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38816>
 2025-12-05 22:30:22 +00:00
Yogesh Mohan Marimuthu
f27b2b8d77 winsys/amdgpu,ac: get eop and csa size,alignment from kernel query
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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38647>
 2025-12-04 16:34:21 +00:00
Yogesh Mohan Marimuthu
f322bc8631 ac: update amdgpu_drm.h for uq metadata query info 
struct drm_amdgpu_info_uq_fw_areas is renamed to drm_amdgpu_info_uq_metadata.
query infor structure for compute and sdma is added.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38647>
 2025-12-04 16:34:20 +00:00
Samuel Pitoiset
b13003133d radv: add radv_cmd_state::emitted_rt_pipeline 
To stop abusing emitted_compute_pipeline for RT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:01 +00:00
Samuel Pitoiset
7d4c49a271 radv: decouple RT and compute dispatches paths 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:01 +00:00
Samuel Pitoiset
fa225de793 radv: constify radv_gfx12_emit_buffered_regs() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:00 +00:00
Samuel Pitoiset
e3aac0d11f radv: remove redundant buffered regs emission for dispatches on GFX12+ 
It's already called few lines above.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:00 +00:00
Samuel Pitoiset
069f60a4e7 radv: enable conservativeRasterizationPostDepthCoverage on GFX10+ when possible
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This seems to work just fine, except on NAVI21, NAVI22 and VANGOGH. It
might be the same issue as has_vrs_ds_export_bug but it's not documented
anywhere. That being said, the CTS tests that fail don't even export
depth or stencil from fragment shaders.

Do not enable this feature on these GPUs to be conservative.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38767>
 2025-12-04 14:16:15 +00:00
Samuel Pitoiset
d1386e167e radv: add support for computeDerivativeGroupQuads on < GFX12 
This was also supported by PAL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38771>
 2025-12-04 13:56:47 +00:00
Marek Olšák
9b011a7344 amd: rename most GFX115x definitions for released chips 
addrlib changes match the original code.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38718>
 2025-12-03 13:29:07 +00:00
Samuel Pitoiset
fda1262eed radv: reduce maxTexelBufferElements to 1<<29 
It's the number of elements. RADV exposes VK_FORMAT_R64_{UINT,SINT}
formats for texel buffers, so the maximum is 1<<29 to fit in the
32-bit bounds checking.

Fixes KHR-GL46.texture_buffer_size_clamping.* with Zink and new VKCTS
dEQP-VK.texture.misc.max_elements.*.

Cc: mesa-stable.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38140>
 2025-12-03 09:31:08 +00:00
David Rosca
2b2914d81f radv/video: Fix AV1 quantization map maxQIndexDelta value 
Fixes: ae6ea69c85 ("radv: Implement VK_KHR_video_encode_quantization_map")
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38745>
 2025-12-02 09:44:35 +00:00
Natalie Vock
a7a4abc8d8 radv: Move VMID reservation to vkCreateDevice
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DXVK's DXGI implementation can create extra instances used for
enumerating physical devices besides the games' instance. When reserving
VMIDs for SPM, the DXGI instances may snatch the VMID reservation early,
making VMID reservation for the instance that actually needs it fail.
This starts being a problem on kernels 6.18+ where only one user may
reserve a VMID at a time.

Move reserving VMIDs to SQTT initialization inside vkCreateDevice so
that only the instances that actually create logical devices try
reserving VMIDs.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38746>
 2025-12-01 17:35:14 +00:00
Benjamin Cheng
fa1fd2413f radv/video: Fix force_integer_mv=1 on intra frame 
According to AV1 spec, force_integer_mv=1 on intra frames. However, VCN
FW does not expect integer mv to be set unless screen content tools are
enabled. This also aligns the code to the radeonsi logic.

Cc: mesa-stable
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38716>
 2025-12-01 17:12:00 +00:00
Samuel Pitoiset
5527b71bce ci: uprev VKCTS main to 211e452358f5cafd14bdd76d78342b62741e94aa 
RADV is the only driver using main.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38651>
 2025-12-01 08:21:38 +01:00
Benjamin Cheng
9e37969179 radv/video: Override direct_spatial_mv_pred to 1
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VCN always uses spatial direct mode.

Cc: mesa-stable
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38686>
 2025-11-30 15:37:46 +00:00
Benjamin Cheng
e5a9b1f28a radv/video: Support two L0 refs on VCN3+ 
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38686>
 2025-11-30 15:37:45 +00:00
Benjamin Cheng
ab56ce154b radv/video: Fix H264/H265 reference selection 
The order of pReferenceSlots is not well-defined by spec. Instead we
need to look at the RefPicList0/1 which provides slot indices.

Cc: mesa-stable
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38686>
 2025-11-30 15:37:44 +00:00