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amd: rename most GFX115x definitions for released chips

Browse source 
addrlib changes match the original code.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38718>
This commit is contained in:
Marek Olšák 2025-11-28 15:33:01 -05:00 • committed by Marge Bot
parent 858364be71
commit 9b011a7344
15 changed files with 42 additions and 42 deletions
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16
src/amd/addrlib/src/amdgpu_asic_addr.h
View file

@ -27,12 +27,12 @@
#define FAMILY_NV 0x8F //# 143 / Navi: 10
#define FAMILY_VGH 0x90 //# 144 / Van Gogh
#define FAMILY_NV3 0x91 //# 145 / Navi: 3x
#define FAMILY_GFX1150 0x96
#define FAMILY_STX 0x96
#define FAMILY_PHX 0x94 //# 148 / Phoenix
#define FAMILY_RMB 0x92 //# 146 / Rembrandt
#define FAMILY_RPL 0x95 //# 149 / Raphael
#define FAMILY_MDN 0x97 //# 151 / Mendocino
#define FAMILY_GFX12 0x98
#define FAMILY_NV4 0x98
// AMDGPU_FAMILY_IS(familyId, familyName)
#define FAMILY_IS(f, fn) (f == FAMILY_##fn)
@ -101,9 +101,9 @@
#define AMDGPU_NAVI31_RANGE 0x01, 0x10 //# 01 <= x < 16
#define AMDGPU_NAVI32_RANGE 0x20, 0xFF //# 32 <= x < 255
#define AMDGPU_NAVI33_RANGE 0x10, 0x20 //# 16 <= x < 32
#define AMDGPU_GFX1150_RANGE 0x01, 0x40 //# 1 <= x < 64
#define AMDGPU_GFX1151_RANGE 0xC0, 0xFF //# 192 <= x < 255
#define AMDGPU_GFX1152_RANGE 0x40, 0x50 //# 64 <= x < 80
#define AMDGPU_STRIX1_RANGE 0x01, 0x40 //# 1 <= x < 64
#define AMDGPU_STRIX_HALO_RANGE 0xC0, 0xFF //# 192 <= x < 255
#define AMDGPU_KRACKAN1_RANGE 0x40, 0x50 //# 64 <= x < 80
#define AMDGPU_GFX1153_RANGE 0x50, 0xC0 //# 80 <= x < 192
#define AMDGPU_PHOENIX1_RANGE 0x01, 0x80 //# 1 <= x < 128
#define AMDGPU_PHOENIX2_RANGE 0x80, 0xC0 //# 128 <= x < 192
@ -181,9 +181,9 @@
#define ASICREV_IS_NAVI31_P(r) ASICREV_IS(r, NAVI31)
#define ASICREV_IS_NAVI32_P(r) ASICREV_IS(r, NAVI32)
#define ASICREV_IS_NAVI33_P(r) ASICREV_IS(r, NAVI33)
#define ASICREV_IS_GFX1150(r) ASICREV_IS(r, GFX1150)
#define ASICREV_IS_GFX1151(r) ASICREV_IS(r, GFX1151)
#define ASICREV_IS_GFX1152(r) ASICREV_IS(r, GFX1152)
#define ASICREV_IS_STRIX1(r) ASICREV_IS(r, STRIX1)
#define ASICREV_IS_STRIX_HALO(r) ASICREV_IS(r, STRIX_HALO)
#define ASICREV_IS_KRACKAN1(r) ASICREV_IS(r, KRACKAN1)
#define ASICREV_IS_GFX1153(r) ASICREV_IS(r, GFX1153)
#define ASICREV_IS_PHOENIX(r) ASICREV_IS(r, PHOENIX)
#define ASICREV_IS_PHOENIX2(r) ASICREV_IS(r, PHOENIX2)

4
src/amd/addrlib/src/core/addrlib.cpp
View file

@ -220,11 +220,11 @@ ADDR_E_RETURNCODE Lib::Create(
pLib = Gfx10HwlInit(&client);
break;
case FAMILY_NV3:
case FAMILY_GFX1150:
case FAMILY_STX:
case FAMILY_PHX:
pLib = Gfx11HwlInit(&client);
break;
case FAMILY_GFX12:
case FAMILY_NV4:
pLib = Gfx12HwlInit(&client);
break;
default:

6
src/amd/addrlib/src/gfx11/gfx11addrlib.cpp
View file

@ -750,9 +750,9 @@ ChipFamily Gfx11Lib::HwlConvertChipFamily(
}
break;
case FAMILY_GFX1150:
case FAMILY_STX:
{
m_settings.isGfx1150 = 1;
m_settings.isStrix = 1;
}
break;
case FAMILY_PHX:
@ -1743,7 +1743,7 @@ UINT_32 Gfx11Lib::GetValidDisplaySwizzleModes(
if (false
|| (m_settings.isPhoenix)
|| (m_settings.isGfx1150)
|| (m_settings.isStrix)
)
{
// Not all GPUs support displaying with 256kB swizzle modes.

2
src/amd/addrlib/src/gfx11/gfx11addrlib.h
View file

@ -34,7 +34,7 @@ struct Gfx11ChipSettings
{
struct
{
UINT_32 isGfx1150 : 1;
UINT_32 isStrix : 1;
UINT_32 isPhoenix : 1;
UINT_32 reserved1 : 30;

4
src/amd/ci/gitlab-ci.yml
View file

@ -359,8 +359,8 @@ radv-fossils:
# RDNA3 (GFX11)
- AMDGPU_GPU_ID="NAVI31"
./install/fossilize-runner.sh
# RDNA3.5 (GFX1150)
- AMDGPU_GPU_ID="GFX1150"
# RDNA3.5 (STRIX1)
- AMDGPU_GPU_ID="STRIX1"
./install/fossilize-runner.sh
############### vkd3d-proton

2
src/amd/common/ac_descriptors.c
View file

@ -1163,7 +1163,7 @@ ac_get_dcc_min_compressed_block_size(const struct radeon_info *info)
* 32B minimum request size. Sometimes a different size is used depending on the data fabric,
* etc.
*/
return info->has_dedicated_vram || info->family == CHIP_GFX1151 ?
return info->has_dedicated_vram || info->family == CHIP_STRIX_HALO ?
V_028C78_MIN_BLOCK_SIZE_32B : V_028C78_MIN_BLOCK_SIZE_64B;
}

10
src/amd/common/ac_gpu_info.c
View file

@ -545,13 +545,13 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
identify_chip2(HAWK_POINT1, PHOENIX);
identify_chip2(HAWK_POINT2, PHOENIX2);
break;
case FAMILY_GFX1150:
identify_chip(GFX1150);
identify_chip(GFX1151);
identify_chip(GFX1152);
case FAMILY_STX:
identify_chip(STRIX1);
identify_chip(STRIX_HALO);
identify_chip(KRACKAN1);
identify_chip(GFX1153);
break;
case FAMILY_GFX12:
case FAMILY_NV4:
identify_chip(GFX1200);
identify_chip(GFX1201);
break;

2
src/amd/common/ac_surface.c
View file

@ -3797,7 +3797,7 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf
/* 0 offsets mean disabled. */
surf->meta_offset = surf->fmask_offset = surf->cmask_offset = surf->display_dcc_offset = 0;
if (info->family_id >= FAMILY_GFX12) {
if (info->family_id >= FAMILY_NV4) {
if (!gfx12_compute_surface(addrlib, info, config, mode, surf))
return ADDR_ERROR;

2
src/amd/common/ac_surface_test.h
View file

@ -233,7 +233,7 @@ static void init_gfx12(struct radeon_info *info)
{
info->family = CHIP_GFX1200;
info->gfx_level = GFX12;
info->family_id = FAMILY_GFX12;
info->family_id = FAMILY_NV4;
info->chip_external_rev = 0x01;
info->has_graphics = true;
info->tcc_cache_line_size = 256;

14
src/amd/common/amd_family.c
View file

@ -56,9 +56,9 @@ const char *ac_get_family_name(enum radeon_family family)
CASE(NAVI33);
CASE(PHOENIX);
CASE(PHOENIX2);
CASE(GFX1150);
CASE(GFX1151);
CASE(GFX1152);
CASE(STRIX1);
CASE(STRIX_HALO);
CASE(KRACKAN1);
CASE(GFX1153);
CASE(GFX1200);
CASE(GFX1201);
@ -72,7 +72,7 @@ enum amd_gfx_level ac_get_gfx_level(enum radeon_family family)
{
if (family >= CHIP_GFX1200)
return GFX12;
if (family >= CHIP_GFX1150)
if (family >= CHIP_STRIX1)
return GFX11_5;
if (family >= CHIP_NAVI31)
return GFX11;
@ -175,11 +175,11 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
case CHIP_PHOENIX:
case CHIP_PHOENIX2:
return "gfx1103";
case CHIP_GFX1150:
case CHIP_STRIX1:
return "gfx1150";
case CHIP_GFX1151:
case CHIP_STRIX_HALO:
return "gfx1151";
case CHIP_GFX1152:
case CHIP_KRACKAN1:
return "gfx1152";
case CHIP_GFX1153:
return "gfx1153";

10
src/amd/common/amd_family.h
View file

@ -123,13 +123,13 @@ enum radeon_family
CHIP_PHOENIX, /* Ryzen Z1 Extreme, Ryzen 7040, Ryzen 8040 */
CHIP_PHOENIX2, /* Ryzen Z1, Ryzen 8040 */
/* GFX11.5 (RDNA 3.5) */
CHIP_GFX1150,
CHIP_GFX1151,
CHIP_GFX1152,
CHIP_STRIX1, /* Ryzen AI 360-375 */
CHIP_STRIX_HALO, /* Ryzen AI MAX */
CHIP_KRACKAN1, /* Ryzen AI 330-350 */
CHIP_GFX1153,
/* GFX12 (RDNA 4) */
CHIP_GFX1200,
CHIP_GFX1201,
CHIP_GFX1200, /* Radeon 9060 */
CHIP_GFX1201, /* Radeon 9070 */
CHIP_LAST,
};

4
src/amd/compiler/aco_ir.cpp
View file

@ -78,7 +78,7 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info,
case GFX10: program->family = CHIP_NAVI10; break;
case GFX10_3: program->family = CHIP_NAVI21; break;
case GFX11: program->family = CHIP_NAVI31; break;
case GFX11_5: program->family = CHIP_GFX1150; break;
case GFX11_5: program->family = CHIP_STRIX1; break;
case GFX12: program->family = CHIP_GFX1200; break;
default: program->family = CHIP_UNKNOWN; break;
}
@ -104,7 +104,7 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info,
program->dev.sgpr_limit =
108; /* includes VCC, which can be treated as s[106-107] on GFX10+ */
if (family == CHIP_NAVI31 || family == CHIP_NAVI32 || family == CHIP_GFX1151 ||
if (family == CHIP_NAVI31 || family == CHIP_NAVI32 || family == CHIP_STRIX_HALO ||
gfx_level >= GFX12) {
program->dev.physical_vgprs = program->wave_size == 32 ? 1536 : 768;
program->dev.vgpr_alloc_granule = program->wave_size == 32 ? 24 : 12;

2
src/amd/compiler/tests/test_insert_waitcnt.cpp
View file

@ -341,7 +341,7 @@ BEGIN_TEST(insert_waitcnt.waw.vmem_types)
END_TEST
BEGIN_TEST(insert_waitcnt.waw.point_sample_accel)
for (radeon_family family : {CHIP_GFX1150, CHIP_GFX1153}) {
for (radeon_family family : {CHIP_STRIX1, CHIP_GFX1153}) {
if (!setup_cs(NULL, GFX11_5, family, family == CHIP_GFX1153 ? "_3" : "_0"))
continue;

4
src/amd/drm-shim/amdgpu_devices.c
View file

@ -2056,8 +2056,8 @@ const struct amdgpu_device amdgpu_devices[] = {
},
},
{
.name = "gfx1150",
.radeon_family = CHIP_GFX1150,
.name = "strix1",
.radeon_family = CHIP_STRIX1,
.hw_ip_gfx = {
.hw_ip_version_major = 11,
.hw_ip_version_minor = 0,

2
src/amd/vulkan/radv_queue.c
View file

@ -824,7 +824,7 @@ radv_emit_graphics(struct radv_device *device, struct radv_cmd_stream *cs)
ac_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, 0);
}
if (pdev->info.family >= CHIP_NAVI31 && pdev->info.family <= CHIP_GFX1150) {
if (pdev->info.family >= CHIP_NAVI31 && pdev->info.family <= CHIP_STRIX1) {
/* Disable SINGLE clear codes on GFX11 (including first GFX11.5 rev) to workaround a hw bug
* with DCC. */
ac_pm4_set_reg(pm4, R_028424_CB_FDCC_CONTROL, S_028424_DISABLE_CONSTANT_ENCODE_SINGLE(1));