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aco/optimizer: propagate fixed registers
Foz-DB Navi48: Totals from 351 (0.36% of 97637) affected shaders: Instrs: 3568192 -> 3567166 (-0.03%) CodeSize: 18890368 -> 18886304 (-0.02%) Latency: 17047945 -> 17048185 (+0.00%); split: -0.00%, +0.00% InvThroughput: 3185739 -> 3185813 (+0.00%); split: -0.00%, +0.00% SClause: 61544 -> 61536 (-0.01%) Copies: 271592 -> 270845 (-0.28%) PreSGPRs: 17186 -> 17094 (-0.54%) PreVGPRs: 21897 -> 21901 (+0.02%) VALU: 2003976 -> 2003980 (+0.00%) SALU: 468403 -> 467664 (-0.16%) Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38830>
This commit is contained in:
Georg Lehmann
Marge Bot
parent
b798ace443
commit
d32dd5e1df
1 changed files with 71 additions and 10 deletions
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@ -46,6 +46,7 @@ enum Label {
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label_scc_invert = 1ull << 5,
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label_scc_needed = 1ull << 6,
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label_extract = 1ull << 7,
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label_phys_reg = 1ull << 8,
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/* These have one label for fp16 and one for fp32/64.
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* 32bit vs 64bit type mismatches are impossible because
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@ -89,12 +90,15 @@ canonicalized_label(unsigned bit_size)
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}
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static_assert((temp_labels & val_labels) == 0, "labels cannot intersect");
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static_assert((temp_labels & label_phys_reg) == 0, "labels cannot intersect");
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static_assert((val_labels & label_phys_reg) == 0, "labels cannot intersect");
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struct ssa_info {
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uint64_t label;
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union {
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uint64_t val;
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Temp temp;
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PhysReg phys_reg;
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};
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Instruction* parent_instr;
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@ -105,11 +109,18 @@ struct ssa_info {
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if (new_label & temp_labels) {
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label &= ~temp_labels;
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label &= ~val_labels; /* temp and val alias */
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label &= ~label_phys_reg; /* temp and phys_reg alias */
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}
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if (new_label & val_labels) {
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label &= ~val_labels;
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label &= ~temp_labels; /* temp and val alias */
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label &= ~label_phys_reg; /* phys_reg and val alias */
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}
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if (new_label & label_phys_reg) {
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label &= ~temp_labels; /* temp and phys_reg alias */
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label &= ~val_labels; /* val and phys_reg alias */
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}
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label |= new_label;
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@ -220,6 +231,22 @@ struct ssa_info {
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void set_extract() { add_label(label_extract); }
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bool is_extract() { return label & label_extract; }
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void set_phys_reg(PhysReg reg)
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{
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assert(reg.byte() == 0);
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add_label(label_phys_reg);
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phys_reg = reg;
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}
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bool is_phys_reg(uint32_t exec_id)
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{
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if (!(label & label_phys_reg))
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return false;
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if (phys_reg != exec && phys_reg != exec_hi)
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return true;
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return exec_id == parent_instr->pass_flags;
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}
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};
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struct opt_ctx {
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@ -1011,6 +1038,8 @@ alu_opt_info_is_valid(opt_ctx& ctx, alu_opt_info& info)
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return false;
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if (is_dpp || format_is(info.format, Format::SDWA))
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return false;
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if (!info.operands[2].op.isTemp())
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return false;
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break;
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case aco_opcode::v_permlane16_b32:
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case aco_opcode::v_permlanex16_b32:
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@ -1123,9 +1152,11 @@ alu_opt_info_is_valid(opt_ctx& ctx, alu_opt_info& info)
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lmask[2] = true;
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info.opcode = aco_opcode::s_fmaak_f32;
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}
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} else if (info.opcode == aco_opcode::s_fmac_f16 && !smask[2]) {
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return false;
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}
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if ((info.opcode == aco_opcode::s_fmac_f16 || info.opcode == aco_opcode::s_fmac_f32) &&
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!info.operands[2].op.isTemp())
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return false;
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}
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return true;
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@ -2022,7 +2053,7 @@ detect_clamp(Instruction* instr, unsigned* clamped_idx)
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}
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bool
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parse_operand(opt_ctx& ctx, Temp tmp, alu_opt_op& op_info, aco_type& type)
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parse_operand(opt_ctx& ctx, Temp tmp, unsigned exec_id, alu_opt_op& op_info, aco_type& type)
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{
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ssa_info info = ctx.info[tmp.id()];
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op_info = {};
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@ -2126,6 +2157,13 @@ parse_operand(opt_ctx& ctx, Temp tmp, alu_opt_op& op_info, aco_type& type)
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return true;
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}
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if (info.is_phys_reg(exec_id)) {
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RegType rtype = info.phys_reg < 256 ? RegType::sgpr : RegType::vgpr;
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RegClass rc = RegClass::get(rtype, tmp.size() * 4);
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op_info.op = Operand(info.phys_reg, rc);
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return true;
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}
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return false;
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}
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@ -2192,12 +2230,20 @@ combine_operand(opt_ctx& ctx, alu_opt_op& inner, const aco_type& inner_type,
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}
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}
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if (outer.op.isTemp())
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if (outer.op.isTemp()) {
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inner.op.setTemp(outer.op.getTemp());
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else if (inner.op.isFixed())
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} else if (inner.op.isFixed()) {
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return false;
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else
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} else {
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bool range16 = inner.op.is16bit();
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bool range24 = inner.op.is24bit();
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inner.op = outer.op;
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if (range16)
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inner.op.set16bit(true);
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else if (range24)
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inner.op.set24bit(true);
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}
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return true;
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}
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@ -2274,7 +2320,7 @@ alu_propagate_temp_const(opt_ctx& ctx, aco_ptr<Instruction>& instr, bool uses_va
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alu_opt_op outer;
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aco_type outer_type;
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if (!parse_operand(ctx, info.operands[i].op.getTemp(), outer, outer_type) ||
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if (!parse_operand(ctx, info.operands[i].op.getTemp(), info.pass_flags, outer, outer_type) ||
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(!uses_valid && outer.f16_to_f32)) {
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operand_mask &= ~BITFIELD_BIT(i);
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continue;
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@ -2351,7 +2397,7 @@ extract_apply_extract(opt_ctx& ctx, aco_ptr<Instruction>& instr)
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alu_opt_op outer;
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aco_type outer_type;
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if (!parse_operand(ctx, instr->operands[0].getTemp(), outer, outer_type))
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if (!parse_operand(ctx, instr->operands[0].getTemp(), instr->pass_flags, outer, outer_type))
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return;
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if (instr->definitions[0].bytes() < 4 && outer.op.isOfType(RegType::sgpr) &&
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@ -2657,8 +2703,15 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr)
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}
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break;
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} else if (info.parent_instr->opcode != aco_opcode::p_create_vector) {
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if (instr->definitions.size() == 2 && instr->operands[0].isTemp() &&
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instr->definitions[0].bytes() == instr->definitions[1].bytes()) {
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if (info.is_phys_reg(instr->pass_flags)) {
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PhysReg reg = ctx.info[instr->operands[0].tempId()].phys_reg;
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for (const Definition& def : instr->definitions) {
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if (reg.byte() == 0)
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ctx.info[def.tempId()].set_phys_reg(reg);
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reg = reg.advance(def.bytes());
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}
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} else if (instr->definitions.size() == 2 && instr->operands[0].isTemp() &&
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instr->definitions[0].bytes() == instr->definitions[1].bytes()) {
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if (instr->operands[0].bytes() == 4) {
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/* D16 subdword split */
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ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp());
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@ -2722,6 +2775,13 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr)
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}
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if (instr->operands[0].bytes() != instr->definitions[0].bytes()) {
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if (ctx.info[instr->operands[0].tempId()].is_phys_reg(instr->pass_flags) &&
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(instr->definitions[0].bytes() * index % 4 == 0)) {
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PhysReg reg = ctx.info[instr->operands[0].tempId()].phys_reg;
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reg = reg.advance(instr->definitions[0].bytes() * index);
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ctx.info[instr->definitions[0].tempId()].set_phys_reg(reg);
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}
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if (instr->operands[0].size() != 1 || !instr->operands[0].isTemp())
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break;
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@ -2772,6 +2832,7 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr)
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ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp());
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} else {
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assert(instr->operands[0].isFixed());
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ctx.info[instr->definitions[0].tempId()].set_phys_reg(instr->operands[0].physReg());
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}
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break;
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case aco_opcode::p_is_helper:
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