Commit graph

16455 commits

Author SHA1 Message Date
Marek Olšák
ea72351a91 r600g: correct texture memory size for Z32F_S8X24 on evergreen 2012-08-04 13:53:07 +02:00
Marek Olšák
c8ff737a18 gallium/u_blitter: remove fallback for stencil copy that all drivers skipped
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-04 13:53:07 +02:00
Marek Olšák
ef1bf6d69e gallium/u_blitter: add ability to blit only depth or only stencil
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-04 13:53:07 +02:00
Marek Olšák
8842678047 gallium: define PIPE_MASK_RGBAZS
I need this and it seems like it could be useful.

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-04 13:53:07 +02:00
Marek Olšák
8aaf6972d1 gallium/u_blitter: minor cleanup
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-04 13:53:07 +02:00
Marek Olšák
67a3e5bc32 gallium/tgsi: fixup texture name strings
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-04 13:53:07 +02:00
Marek Olšák
6c420b1668 gallium/u_blitter: set sample mask to ~0
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-04 13:53:07 +02:00
Marek Olšák
9d1ef354f9 gallium/u_blit: bail out if src is a multisample texture
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-04 13:53:07 +02:00
Marek Olšák
6b3f1ae12b gallium/u_blit: check nr_samples before using resource_copy_region
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-04 13:53:07 +02:00
Marek Olšák
e7689303a8 gallium: set sample mask to ~0 for clear, blit and gen_mipmap
The sample mask affects single-sampled rendering too (it's orthogonal
to the color mask).

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-04 13:53:06 +02:00
Dave Airlie
cd97a5f660 r600g: fix F2U opcode translation
Signed-off-by: Marek Olšák <maraeo@gmail.com>
2012-08-04 13:45:27 +02:00
Vinson Lee
5bce0b5175 draw: Ensure channel in convert_to_soa is initialized.
Fixes uninitialized pointer read defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-03 22:28:31 -07:00
Vinson Lee
9d36b3abfd u_blitter: Move a pointer dereference after null check.
Fixes dereference before null check defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-08-03 22:27:13 -07:00
Matt Turner
fb85558ab1 Use C99 NAN and INFINITY macros 2012-08-03 15:02:09 -07:00
Brian Paul
65da837fcf gallium/tests/trivial: updates for CSO interface changes 2012-08-03 11:58:43 -06:00
Brian Paul
c61d3fe8bd st/xorg: updates for CSO interface changes 2012-08-03 11:56:36 -06:00
Brian Paul
459dd56897 st/xa: updates for CSO interface changes 2012-08-03 11:56:28 -06:00
Brian Paul
3d1bec5d9a vega: fix build breakage from cso sampler/view changes 2012-08-03 08:33:23 -06:00
Brian Paul
832706a80b cso: remove unreachable break statements 2012-08-03 07:16:35 -06:00
Brian Paul
076e5eacf1 cso: 80-column wrapping, remove trailing whitespace, etc 2012-08-03 07:16:35 -06:00
Brian Paul
ea6f035ae9 gallium: consolidate CSO sampler and sampler_view functions
Merge the vertex/fragment versions of the cso_set/save/restore_samplers()
functions.  Now we pass the shader stage (PIPE_SHADER_x) to the function
to indicate vertex/fragment/geometry samplers.  For example:

cso_single_sampler(cso, PIPE_SHADER_FRAGMENT, unit, sampler);

This results in quite a bit of code reduction, fewer CSO functions and
support for geometry shaders.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-08-03 07:16:35 -06:00
Tom Stellard
f6ad8b45c2 radeon/llvm: Add $(LLVM_LDFLAGS) to the loader linker flags 2012-08-02 20:12:11 +00:00
Tom Stellard
4a89a20717 radeon/llvm: Add support for more f32 CMP instructions on SI 2012-08-02 20:12:11 +00:00
Tom Stellard
a35eea7868 radeon/llvm: Add support for fneg on SI 2012-08-02 20:12:10 +00:00
Tom Stellard
4104bae063 radeon/llvm: Add support for fp_to_sint on SI 2012-08-02 20:12:10 +00:00
Tom Stellard
f7fcaa07df radeon/llvm: Remove CMOVLOG DAG node 2012-08-02 20:12:06 +00:00
Tom Stellard
a5ac8ee2c5 radeonsi: Properly initialize si_shader_ctx.radeon_bld 2012-08-02 13:21:30 -04:00
Michel Dänzer
c2bae6b91d radeonsi: Handle TGSI TXP opcode.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-08-02 18:38:47 +02:00
Michel Dänzer
93b4f1f97e radeonsi: Handle TGSI DIV opcode.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-08-02 18:38:16 +02:00
Brian Paul
daf4254d07 svga: remove questionable INLINE qualifiers 2012-08-02 09:40:41 -06:00
Brian Paul
421f134028 svga: sort #includes 2012-08-02 09:40:40 -06:00
Brian Paul
81f2f3f65c svga: add some comments in svga_screen_cache.c 2012-08-02 09:40:40 -06:00
Brian Paul
4b5a5898b1 svga: whitespace, formatting fixes 2012-08-02 09:40:40 -06:00
Brian Paul
bcd8d9713d svga: remove unneeded 'struct svga_screen' declarations 2012-08-02 09:40:40 -06:00
Christian König
41625afa2f radeonsi: initial VDPAU target
Windowed speed is of course way to slow, but fullscreen
works like a charm now.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-08-02 15:15:23 +02:00
Christian König
a3c6607be1 radeon/llvm: fix fp immediates on SI
I don't know if this is a good idea, but it
fixes the problem at hand.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-08-02 15:15:00 +02:00
Christian König
250b7fdd26 radeonsi: fix TEX writemask
Using the writemask in the sampler results in packet
VGPRS. For now just sample all components and let
llvm chose the right one.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-08-02 12:05:33 +02:00
Christian König
3508815d17 radeonsi: fix shader param and color count
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-08-02 11:22:57 +02:00
Christian König
92b96a883f radeonsi: fix texture loads from sampler > 0
The backend is multiplying the offset by the numbers of
elements anyway, so doing it twice just makes everything
crash.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-08-02 11:22:52 +02:00
Christian König
9b7dc5e81c radeonsi: disable tiling until we fixed all bugs
Currently there are more important things to worry about.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-08-02 11:22:40 +02:00
Vinson Lee
8734584952 scons: Add support for Intel Compiler.
The patch makes the SCons build with Intel Compiler successful.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-01 21:28:47 -07:00
Christoph Bumiller
8592933de8 nv50,nvc0: make resolve sampler objects allow sRGB conversion
Just figured out what that bit does.

Note: It's converted back to sRGB on write, so no effective
conversion occurs.
2012-08-01 15:39:46 +02:00
Christoph Bumiller
6286d9810b Revert "gallium: specify resource_resolve destination via a pipe_surface"
This reverts commit 5d5af7d359.

It turns out the issue this was supposed to fix merely counter-acted
a bug in the hardware driver that I wasn't aware of.

The resource_resolve is not supposed to do sRGB conversion, period.
(This would violate the requirement that source and destination must
be of the same format).
2012-08-01 15:39:46 +02:00
Christian König
6574fe3c4a radeon/llvm: fix calculation of max register number
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-08-01 11:15:06 +02:00
Tom Stellard
a488fdd3d9 radeon/llvm: Add pseudo-support for 64-bit immediate types on SI
SI does not support 64-bit immediates natively, but llvm will generate
i64 immediates when indexing loads and stores (since SI has 64-bit
pointers).  The i64 indices will always be small enough to fit into
32-bits (i.e. the high 32 bits will always be all zeros), so we can
treat these index values as 32-bits.
2012-07-31 20:19:21 +00:00
Tom Stellard
be46874281 radeon/llvm: Fix incorrect return value in SelectADDRReg()
We need to return true when we match the pattern.
2012-07-31 20:19:20 +00:00
Tom Stellard
056b77ca22 radeon/llvm: Move SMRD IMM pattern before SMRD SGPR pattern
In tablegen, if two patterns match, the one that comes first in the file
is given preference.  We want the SMRD IMM pattern to be given
preference, because it encodes the pointer offset in its immediate
field, which saves us an add instruction.
2012-07-31 20:19:20 +00:00
Vinson Lee
2faa2b4f7e gallium/util: Use GCC built-in functions for NaN and infinity.
This patch fixes this build failure with Intel Compiler.

src/gallium/auxiliary/util/u_format_tests.c(903): error: floating-point operation result is out of range
     {PIPE_FORMAT_R16_FLOAT, PACKED_1x16(0xffff), PACKED_1x16(0x7c01), UNPACKED_1x1(        NAN, 0.0, 0.0, 1.0)},

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-07-30 23:27:19 -07:00
Tom Stellard
cd0949eb28 radeon/llvm: Cleanup AMDIL.h 2012-07-30 21:10:14 +00:00
Tom Stellard
2f921101c0 radeon/llvm: Rename all AMDIL* classes to AMDGPU* 2012-07-30 21:10:14 +00:00