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radeonsi: Handle TGSI DIV opcode.

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Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
Michel Dänzer 2012-08-02 17:30:44 +02:00 • committed by Michel Dänzer
parent daf4254d07
commit 93b4f1f97e
1 changed files with 5 additions and 0 deletions
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5
src/gallium/drivers/radeon/SIInstructions.td
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@ -1088,6 +1088,11 @@ def : Pat <
/* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */
def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_F32_e32, VReg_32>;
def : Pat <
(int_AMDGPU_div AllReg_32:$src0, AllReg_32:$src1),
(V_MUL_LEGACY_F32_e32 AllReg_32:$src0, (V_RCP_LEGACY_F32_e32 AllReg_32:$src1))
>;
/********** ================== **********/
/********** VOP3 Patterns **********/
/********** ================== **********/