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radeon/llvm: Rename all AMDIL* classes to AMDGPU*

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This commit is contained in:
Tom Stellard 2012-07-30 15:57:50 +00:00
parent b72ab79d73
commit 2f921101c0
30 changed files with 496 additions and 496 deletions
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10
src/gallium/drivers/radeon/AMDGPUSubtarget.cpp
View file

@ -13,7 +13,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
InstrItins = getInstrItineraryForCPU(CPU);
memset(CapsOverride, 0, sizeof(*CapsOverride)
* AMDILDeviceInfo::MaxNumberCapabilities);
* AMDGPUDeviceInfo::MaxNumberCapabilities);
// Default card
StringRef GPU = CPU;
mIs64bit = false;
@ -22,7 +22,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
mDefaultSize[2] = 1;
ParseSubtargetFeatures(GPU, FS);
mDevName = GPU;
mDevice = AMDILDeviceInfo::getDeviceFromName(mDevName, this, mIs64bit);
mDevice = AMDGPUDeviceInfo::getDeviceFromName(mDevName, this, mIs64bit);
}
AMDGPUSubtarget::~AMDGPUSubtarget()
@ -31,9 +31,9 @@ AMDGPUSubtarget::~AMDGPUSubtarget()
}
bool
AMDGPUSubtarget::isOverride(AMDILDeviceInfo::Caps caps) const
AMDGPUSubtarget::isOverride(AMDGPUDeviceInfo::Caps caps) const
{
assert(caps < AMDILDeviceInfo::MaxNumberCapabilities &&
assert(caps < AMDGPUDeviceInfo::MaxNumberCapabilities &&
"Caps index is out of bounds!");
return CapsOverride[caps];
}
@ -75,7 +75,7 @@ AMDGPUSubtarget::getDeviceName() const
{
return mDevName;
}
const AMDILDevice *
const AMDGPUDevice *
AMDGPUSubtarget::device() const
{
return mDevice;

8
src/gallium/drivers/radeon/AMDGPUSubtarget.h
View file

@ -28,8 +28,8 @@ namespace llvm {
class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo
{
private:
bool CapsOverride[AMDILDeviceInfo::MaxNumberCapabilities];
const AMDILDevice *mDevice;
bool CapsOverride[AMDGPUDeviceInfo::MaxNumberCapabilities];
const AMDGPUDevice *mDevice;
size_t mDefaultSize[3];
size_t mMinimumSize[3];
std::string mDevName;
@ -46,12 +46,12 @@ public:
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
virtual void ParseSubtargetFeatures(llvm::StringRef CPU, llvm::StringRef FS);
bool isOverride(AMDILDeviceInfo::Caps) const;
bool isOverride(AMDGPUDeviceInfo::Caps) const;
bool is64bit() const;
// Helper functions to simplify if statements
bool isTargetELF() const;
const AMDILDevice* device() const;
const AMDGPUDevice* device() const;
std::string getDataLayout() const;
std::string getDeviceName() const;
virtual size_t getDefaultSize(uint32_t dim) const;

16
src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
View file

@ -55,7 +55,7 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
{
// TLInfo uses InstrInfo so it must be initialized after.
if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
InstrInfo = new R600InstrInfo(*this);
TLInfo = new R600TargetLowering(*this);
} else {
@ -82,7 +82,7 @@ bool AMDGPUTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
std::string gpu = STM.getDeviceName();
if (gpu == "SI") {
PM.add(createSICodeEmitterPass(Out));
} else if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
} else if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
PM.add(createR600CodeEmitterPass(Out));
} else {
abort();
@ -120,7 +120,7 @@ bool
AMDGPUPassConfig::addPreISel()
{
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
PM->add(createR600KernelParametersPass(
getAMDGPUTargetMachine().getTargetData()));
}
@ -128,15 +128,15 @@ AMDGPUPassConfig::addPreISel()
}
bool AMDGPUPassConfig::addInstSelector() {
PM->add(createAMDILPeepholeOpt(*TM));
PM->add(createAMDILISelDag(getAMDGPUTargetMachine()));
PM->add(createAMDGPUPeepholeOpt(*TM));
PM->add(createAMDGPUISelDag(getAMDGPUTargetMachine()));
return false;
}
bool AMDGPUPassConfig::addPreRegAlloc() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
PM->add(createSIAssignInterpRegsPass(*TM));
}
PM->add(createAMDGPUConvertToISAPass(*TM));
@ -152,8 +152,8 @@ bool AMDGPUPassConfig::addPreSched2() {
}
bool AMDGPUPassConfig::addPreEmitPass() {
PM->add(createAMDILCFGPreparationPass(*TM));
PM->add(createAMDILCFGStructurizerPass(*TM));
PM->add(createAMDGPUCFGPreparationPass(*TM));
PM->add(createAMDGPUCFGStructurizerPass(*TM));
return false;
}

8
src/gallium/drivers/radeon/AMDGPUTargetMachine.h
View file

@ -30,8 +30,8 @@ class AMDGPUTargetMachine : public LLVMTargetMachine {
AMDGPUSubtarget Subtarget;
const TargetData DataLayout;
AMDILFrameLowering FrameLowering;
AMDILIntrinsicInfo IntrinsicInfo;
AMDGPUFrameLowering FrameLowering;
AMDGPUIntrinsicInfo IntrinsicInfo;
const AMDGPUInstrInfo * InstrInfo;
AMDGPUTargetLowering * TLInfo;
const InstrItineraryData* InstrItins;
@ -44,10 +44,10 @@ public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
~AMDGPUTargetMachine();
virtual const AMDILFrameLowering* getFrameLowering() const {
virtual const AMDGPUFrameLowering* getFrameLowering() const {
return &FrameLowering;
}
virtual const AMDILIntrinsicInfo* getIntrinsicInfo() const {
virtual const AMDGPUIntrinsicInfo* getIntrinsicInfo() const {
return &IntrinsicInfo;
}
virtual const AMDGPUInstrInfo *getInstrInfo() const {return InstrInfo;}

14
src/gallium/drivers/radeon/AMDIL.h
View file

@ -81,7 +81,7 @@ const unsigned int RESERVED_FUNCS = 1024;
#define AMDIL_OPT_LEVEL_VAR_NO_COMMA
namespace llvm {
class AMDILInstrPrinter;
class AMDGPUInstrPrinter;
class FunctionPass;
class MCAsmInfo;
class raw_ostream;
@ -90,15 +90,15 @@ class TargetMachine;
/// Instruction selection passes.
FunctionPass*
createAMDILISelDag(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
createAMDGPUISelDag(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
FunctionPass*
createAMDILPeepholeOpt(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
createAMDGPUPeepholeOpt(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
/// Pre emit passes.
FunctionPass*
createAMDILCFGPreparationPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
createAMDGPUCFGPreparationPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
FunctionPass*
createAMDILCFGStructurizerPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
createAMDGPUCFGStructurizerPass(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
extern Target TheAMDILTarget;
extern Target TheAMDGPUTarget;
@ -114,7 +114,7 @@ namespace llvm {
/// however on the GPU, each address space points to
/// a seperate piece of memory that is unique from other
/// memory locations.
namespace AMDILAS {
namespace AMDGPUAS {
enum AddressSpaces {
PRIVATE_ADDRESS = 0, // Address space for private memory.
GLOBAL_ADDRESS = 1, // Address space for global memory (RAT0, VTX0).
@ -165,7 +165,7 @@ typedef union ResourceRec {
unsigned short u16all;
} InstrResEnc;
} // namespace AMDILAS
} // namespace AMDGPUAS
} // end namespace llvm
#endif // AMDIL_H_

66
src/gallium/drivers/radeon/AMDIL7XXDevice.cpp
View file

@ -15,7 +15,7 @@
using namespace llvm;
AMDIL7XXDevice::AMDIL7XXDevice(AMDGPUSubtarget *ST) : AMDILDevice(ST)
AMDGPU7XXDevice::AMDGPU7XXDevice(AMDGPUSubtarget *ST) : AMDGPUDevice(ST)
{
setCaps();
std::string name = mSTM->getDeviceName();
@ -28,34 +28,34 @@ AMDIL7XXDevice::AMDIL7XXDevice(AMDGPUSubtarget *ST) : AMDILDevice(ST)
}
}
AMDIL7XXDevice::~AMDIL7XXDevice()
AMDGPU7XXDevice::~AMDGPU7XXDevice()
{
}
void AMDIL7XXDevice::setCaps()
void AMDGPU7XXDevice::setCaps()
{
mSWBits.set(AMDILDeviceInfo::LocalMem);
mSWBits.set(AMDGPUDeviceInfo::LocalMem);
}
size_t AMDIL7XXDevice::getMaxLDSSize() const
size_t AMDGPU7XXDevice::getMaxLDSSize() const
{
if (usesHardware(AMDILDeviceInfo::LocalMem)) {
if (usesHardware(AMDGPUDeviceInfo::LocalMem)) {
return MAX_LDS_SIZE_700;
}
return 0;
}
size_t AMDIL7XXDevice::getWavefrontSize() const
size_t AMDGPU7XXDevice::getWavefrontSize() const
{
return AMDILDevice::HalfWavefrontSize;
return AMDGPUDevice::HalfWavefrontSize;
}
uint32_t AMDIL7XXDevice::getGeneration() const
uint32_t AMDGPU7XXDevice::getGeneration() const
{
return AMDILDeviceInfo::HD4XXX;
return AMDGPUDeviceInfo::HD4XXX;
}
uint32_t AMDIL7XXDevice::getResourceID(uint32_t DeviceID) const
uint32_t AMDGPU7XXDevice::getResourceID(uint32_t DeviceID) const
{
switch (DeviceID) {
default:
@ -67,18 +67,18 @@ uint32_t AMDIL7XXDevice::getResourceID(uint32_t DeviceID) const
case ARENA_UAV_ID:
break;
case LDS_ID:
if (usesHardware(AMDILDeviceInfo::LocalMem)) {
if (usesHardware(AMDGPUDeviceInfo::LocalMem)) {
return DEFAULT_LDS_ID;
}
break;
case SCRATCH_ID:
if (usesHardware(AMDILDeviceInfo::PrivateMem)) {
if (usesHardware(AMDGPUDeviceInfo::PrivateMem)) {
return DEFAULT_SCRATCH_ID;
}
break;
case GDS_ID:
assert(0 && "GDS UAV ID is not supported on this chip");
if (usesHardware(AMDILDeviceInfo::RegionMem)) {
if (usesHardware(AMDGPUDeviceInfo::RegionMem)) {
return DEFAULT_GDS_ID;
}
break;
@ -87,56 +87,56 @@ uint32_t AMDIL7XXDevice::getResourceID(uint32_t DeviceID) const
return 0;
}
uint32_t AMDIL7XXDevice::getMaxNumUAVs() const
uint32_t AMDGPU7XXDevice::getMaxNumUAVs() const
{
return 1;
}
AsmPrinter*
AMDIL7XXDevice::getAsmPrinter(TargetMachine& TM, MCStreamer &Streamer) const
AMDGPU7XXDevice::getAsmPrinter(TargetMachine& TM, MCStreamer &Streamer) const
{
#ifdef UPSTREAM_LLVM
return new AMDIL7XXAsmPrinter(TM, Streamer);
return new AMDGPU7XXAsmPrinter(TM, Streamer);
#else
return NULL;
#endif
}
AMDIL770Device::AMDIL770Device(AMDGPUSubtarget *ST): AMDIL7XXDevice(ST)
AMDGPU770Device::AMDGPU770Device(AMDGPUSubtarget *ST): AMDGPU7XXDevice(ST)
{
setCaps();
}
AMDIL770Device::~AMDIL770Device()
AMDGPU770Device::~AMDGPU770Device()
{
}
void AMDIL770Device::setCaps()
void AMDGPU770Device::setCaps()
{
if (mSTM->isOverride(AMDILDeviceInfo::DoubleOps)) {
mSWBits.set(AMDILDeviceInfo::FMA);
mHWBits.set(AMDILDeviceInfo::DoubleOps);
if (mSTM->isOverride(AMDGPUDeviceInfo::DoubleOps)) {
mSWBits.set(AMDGPUDeviceInfo::FMA);
mHWBits.set(AMDGPUDeviceInfo::DoubleOps);
}
mSWBits.set(AMDILDeviceInfo::BarrierDetect);
mHWBits.reset(AMDILDeviceInfo::LongOps);
mSWBits.set(AMDILDeviceInfo::LongOps);
mSWBits.set(AMDILDeviceInfo::LocalMem);
mSWBits.set(AMDGPUDeviceInfo::BarrierDetect);
mHWBits.reset(AMDGPUDeviceInfo::LongOps);
mSWBits.set(AMDGPUDeviceInfo::LongOps);
mSWBits.set(AMDGPUDeviceInfo::LocalMem);
}
size_t AMDIL770Device::getWavefrontSize() const
size_t AMDGPU770Device::getWavefrontSize() const
{
return AMDILDevice::WavefrontSize;
return AMDGPUDevice::WavefrontSize;
}
AMDIL710Device::AMDIL710Device(AMDGPUSubtarget *ST) : AMDIL7XXDevice(ST)
AMDGPU710Device::AMDGPU710Device(AMDGPUSubtarget *ST) : AMDGPU7XXDevice(ST)
{
}
AMDIL710Device::~AMDIL710Device()
AMDGPU710Device::~AMDGPU710Device()
{
}
size_t AMDIL710Device::getWavefrontSize() const
size_t AMDGPU710Device::getWavefrontSize() const
{
return AMDILDevice::QuarterWavefrontSize;
return AMDGPUDevice::QuarterWavefrontSize;
}

32
src/gallium/drivers/radeon/AMDIL7XXDevice.h
View file

@ -25,14 +25,14 @@ class AMDGPUSubtarget;
// 7XX generation of devices and their respective sub classes
//===----------------------------------------------------------------------===//
// The AMDIL7XXDevice class represents the generic 7XX device. All 7XX
// devices are derived from this class. The AMDIL7XX device will only
// The AMDGPU7XXDevice class represents the generic 7XX device. All 7XX
// devices are derived from this class. The AMDGPU7XX device will only
// support the minimal features that are required to be considered OpenCL 1.0
// compliant and nothing more.
class AMDIL7XXDevice : public AMDILDevice {
class AMDGPU7XXDevice : public AMDGPUDevice {
public:
AMDIL7XXDevice(AMDGPUSubtarget *ST);
virtual ~AMDIL7XXDevice();
AMDGPU7XXDevice(AMDGPUSubtarget *ST);
virtual ~AMDGPU7XXDevice();
virtual size_t getMaxLDSSize() const;
virtual size_t getWavefrontSize() const;
virtual uint32_t getGeneration() const;
@ -43,30 +43,30 @@ public:
protected:
virtual void setCaps();
}; // AMDIL7XXDevice
}; // AMDGPU7XXDevice
// The AMDIL770Device class represents the RV770 chip and it's
// The AMDGPU770Device class represents the RV770 chip and it's
// derivative cards. The difference between this device and the base
// class is this device device adds support for double precision
// and has a larger wavefront size.
class AMDIL770Device : public AMDIL7XXDevice {
class AMDGPU770Device : public AMDGPU7XXDevice {
public:
AMDIL770Device(AMDGPUSubtarget *ST);
virtual ~AMDIL770Device();
AMDGPU770Device(AMDGPUSubtarget *ST);
virtual ~AMDGPU770Device();
virtual size_t getWavefrontSize() const;
private:
virtual void setCaps();
}; // AMDIL770Device
}; // AMDGPU770Device
// The AMDIL710Device class derives from the 7XX base class, but this
// The AMDGPU710Device class derives from the 7XX base class, but this
// class is a smaller derivative, so we need to overload some of the
// functions in order to correctly specify this information.
class AMDIL710Device : public AMDIL7XXDevice {
class AMDGPU710Device : public AMDGPU7XXDevice {
public:
AMDIL710Device(AMDGPUSubtarget *ST);
virtual ~AMDIL710Device();
AMDGPU710Device(AMDGPUSubtarget *ST);
virtual ~AMDGPU710Device();
virtual size_t getWavefrontSize() const;
}; // AMDIL710Device
}; // AMDGPU710Device
} // namespace llvm
#endif // _AMDILDEVICEIMPL_H_

18
src/gallium/drivers/radeon/AMDILBase.td
View file

@ -19,35 +19,35 @@ def NullALU : InstrItinClass;
// AMDIL Subtarget features.
//===----------------------------------------------------------------------===//
def FeatureFP64 : SubtargetFeature<"fp64",
"CapsOverride[AMDILDeviceInfo::DoubleOps]",
"CapsOverride[AMDGPUDeviceInfo::DoubleOps]",
"true",
"Enable 64bit double precision operations">;
def FeatureByteAddress : SubtargetFeature<"byte_addressable_store",
"CapsOverride[AMDILDeviceInfo::ByteStores]",
"CapsOverride[AMDGPUDeviceInfo::ByteStores]",
"true",
"Enable byte addressable stores">;
def FeatureBarrierDetect : SubtargetFeature<"barrier_detect",
"CapsOverride[AMDILDeviceInfo::BarrierDetect]",
"CapsOverride[AMDGPUDeviceInfo::BarrierDetect]",
"true",
"Enable duplicate barrier detection(HD5XXX or later).">;
def FeatureImages : SubtargetFeature<"images",
"CapsOverride[AMDILDeviceInfo::Images]",
"CapsOverride[AMDGPUDeviceInfo::Images]",
"true",
"Enable image functions">;
def FeatureMultiUAV : SubtargetFeature<"multi_uav",
"CapsOverride[AMDILDeviceInfo::MultiUAV]",
"CapsOverride[AMDGPUDeviceInfo::MultiUAV]",
"true",
"Generate multiple UAV code(HD5XXX family or later)">;
def FeatureMacroDB : SubtargetFeature<"macrodb",
"CapsOverride[AMDILDeviceInfo::MacroDB]",
"CapsOverride[AMDGPUDeviceInfo::MacroDB]",
"true",
"Use internal macrodb, instead of macrodb in driver">;
def FeatureNoAlias : SubtargetFeature<"noalias",
"CapsOverride[AMDILDeviceInfo::NoAlias]",
"CapsOverride[AMDGPUDeviceInfo::NoAlias]",
"true",
"assert that all kernel argument pointers are not aliased">;
def FeatureNoInline : SubtargetFeature<"no-inline",
"CapsOverride[AMDILDeviceInfo::NoInline]",
"CapsOverride[AMDGPUDeviceInfo::NoInline]",
"true",
"specify whether to not inline functions">;
@ -61,7 +61,7 @@ def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
"false",
"Specify if 64bit sized pointers with 32bit addressing should be used.">;
def FeatureDebug : SubtargetFeature<"debug",
"CapsOverride[AMDILDeviceInfo::Debug]",
"CapsOverride[AMDGPUDeviceInfo::Debug]",
"true",
"Debug mode is enabled, so disable hardware accelerated address spaces.">;
def FeatureDumpCode : SubtargetFeature <"DumpCode",

108
src/gallium/drivers/radeon/AMDILCFGStructurizer.cpp
View file

@ -430,7 +430,7 @@ bool CFGStructurizer<PassT>::prepare(FuncT &func, PassT &pass,
//to do, if not reducible flow graph, make it so ???
if (DEBUGME) {
errs() << "AMDILCFGStructurizer::prepare\n";
errs() << "AMDGPUCFGStructurizer::prepare\n";
//func.viewCFG();
//func.viewCFGOnly();
//func.dump();
@ -517,7 +517,7 @@ bool CFGStructurizer<PassT>::run(FuncT &func, PassT &pass,
//Assume reducible CFG...
if (DEBUGME) {
errs() << "AMDILCFGStructurizer::run\n";
errs() << "AMDGPUCFGStructurizer::run\n";
//errs() << func.getFunction()->getNameStr() << "\n";
func.viewCFG();
//func.viewCFGOnly();
@ -2104,7 +2104,7 @@ void CFGStructurizer<PassT>::migrateInstruction(BlockT *srcBlk,
BlockT *dstBlk,
InstrIterator insertPos) {
InstrIterator spliceEnd;
//look for the input branchinstr, not the AMDIL branchinstr
//look for the input branchinstr, not the AMDGPU branchinstr
InstrT *branchInstr = CFGTraits::getNormalBlockBranchInstr(srcBlk);
if (branchInstr == NULL) {
if (DEBUGME) {
@ -2609,7 +2609,7 @@ CFGStructurizer<PassT>::findNearestCommonPostDom
//===----------------------------------------------------------------------===//
//
// CFGStructurizer for AMDIL
// CFGStructurizer for AMDGPU
//
//===----------------------------------------------------------------------===//
@ -2618,7 +2618,7 @@ using namespace llvmCFGStruct;
namespace llvm
{
class AMDILCFGStructurizer : public MachineFunctionPass
class AMDGPUCFGStructurizer : public MachineFunctionPass
{
public:
typedef MachineInstr InstructionType;
@ -2636,24 +2636,24 @@ protected:
const AMDGPURegisterInfo *TRI;
public:
AMDILCFGStructurizer(char &pid, TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
AMDGPUCFGStructurizer(char &pid, TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
const TargetInstrInfo *getTargetInstrInfo() const;
//bool runOnMachineFunction(MachineFunction &F);
private:
}; //end of class AMDILCFGStructurizer
}; //end of class AMDGPUCFGStructurizer
//char AMDILCFGStructurizer::ID = 0;
//char AMDGPUCFGStructurizer::ID = 0;
} //end of namespace llvm
AMDILCFGStructurizer::AMDILCFGStructurizer(char &pid, TargetMachine &tm
AMDGPUCFGStructurizer::AMDGPUCFGStructurizer(char &pid, TargetMachine &tm
AMDIL_OPT_LEVEL_DECL)
: MachineFunctionPass(pid), TM(tm), TII(tm.getInstrInfo()),
TRI(static_cast<const AMDGPURegisterInfo *>(tm.getRegisterInfo())
) {
}
const TargetInstrInfo *AMDILCFGStructurizer::getTargetInstrInfo() const {
const TargetInstrInfo *AMDGPUCFGStructurizer::getTargetInstrInfo() const {
return TII;
}
//===----------------------------------------------------------------------===//
@ -2667,13 +2667,13 @@ using namespace llvmCFGStruct;
namespace llvm
{
class AMDILCFGPrepare : public AMDILCFGStructurizer
class AMDGPUCFGPrepare : public AMDGPUCFGStructurizer
{
public:
static char ID;
public:
AMDILCFGPrepare(TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
AMDGPUCFGPrepare(TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
virtual const char *getPassName() const;
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
@ -2682,20 +2682,20 @@ public:
private:
}; //end of class AMDILCFGPrepare
}; //end of class AMDGPUCFGPrepare
char AMDILCFGPrepare::ID = 0;
char AMDGPUCFGPrepare::ID = 0;
} //end of namespace llvm
AMDILCFGPrepare::AMDILCFGPrepare(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
: AMDILCFGStructurizer(ID, tm AMDIL_OPT_LEVEL_VAR)
AMDGPUCFGPrepare::AMDGPUCFGPrepare(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
: AMDGPUCFGStructurizer(ID, tm AMDIL_OPT_LEVEL_VAR)
{
}
const char *AMDILCFGPrepare::getPassName() const {
const char *AMDGPUCFGPrepare::getPassName() const {
return "AMD IL Control Flow Graph Preparation Pass";
}
void AMDILCFGPrepare::getAnalysisUsage(AnalysisUsage &AU) const {
void AMDGPUCFGPrepare::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<MachineFunctionAnalysis>();
AU.addRequired<MachineFunctionAnalysis>();
AU.addRequired<MachineDominatorTree>();
@ -2714,34 +2714,34 @@ using namespace llvmCFGStruct;
namespace llvm
{
class AMDILCFGPerform : public AMDILCFGStructurizer
class AMDGPUCFGPerform : public AMDGPUCFGStructurizer
{
public:
static char ID;
public:
AMDILCFGPerform(TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
AMDGPUCFGPerform(TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
virtual const char *getPassName() const;
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
bool runOnMachineFunction(MachineFunction &F);
private:
}; //end of class AMDILCFGPerform
}; //end of class AMDGPUCFGPerform
char AMDILCFGPerform::ID = 0;
char AMDGPUCFGPerform::ID = 0;
} //end of namespace llvm
AMDILCFGPerform::AMDILCFGPerform(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
: AMDILCFGStructurizer(ID, tm AMDIL_OPT_LEVEL_VAR)
AMDGPUCFGPerform::AMDGPUCFGPerform(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
: AMDGPUCFGStructurizer(ID, tm AMDIL_OPT_LEVEL_VAR)
{
}
const char *AMDILCFGPerform::getPassName() const {
const char *AMDGPUCFGPerform::getPassName() const {
return "AMD IL Control Flow Graph structurizer Pass";
}
void AMDILCFGPerform::getAnalysisUsage(AnalysisUsage &AU) const {
void AMDGPUCFGPerform::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<MachineFunctionAnalysis>();
AU.addRequired<MachineFunctionAnalysis>();
AU.addRequired<MachineDominatorTree>();
@ -2751,15 +2751,15 @@ void AMDILCFGPerform::getAnalysisUsage(AnalysisUsage &AU) const {
//===----------------------------------------------------------------------===//
//
// CFGStructTraits<AMDILCFGStructurizer>
// CFGStructTraits<AMDGPUCFGStructurizer>
//
//===----------------------------------------------------------------------===//
namespace llvmCFGStruct
{
// this class is tailor to the AMDIL backend
// this class is tailor to the AMDGPU backend
template<>
struct CFGStructTraits<AMDILCFGStructurizer>
struct CFGStructTraits<AMDGPUCFGStructurizer>
{
typedef int RegiT;
@ -2971,12 +2971,12 @@ struct CFGStructTraits<AMDILCFGStructurizer>
}//getInstrPos
static MachineInstr *insertInstrBefore(MachineBasicBlock *blk, int newOpcode,
AMDILCFGStructurizer *passRep) {
AMDGPUCFGStructurizer *passRep) {
return insertInstrBefore(blk,newOpcode,passRep,DebugLoc());
} //insertInstrBefore
static MachineInstr *insertInstrBefore(MachineBasicBlock *blk, int newOpcode,
AMDILCFGStructurizer *passRep, DebugLoc DL) {
AMDGPUCFGStructurizer *passRep, DebugLoc DL) {
const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
MachineInstr *newInstr =
blk->getParent()->CreateMachineInstr(tii->get(newOpcode), DL);
@ -2994,12 +2994,12 @@ struct CFGStructTraits<AMDILCFGStructurizer>
} //insertInstrBefore
static void insertInstrEnd(MachineBasicBlock *blk, int newOpcode,
AMDILCFGStructurizer *passRep) {
AMDGPUCFGStructurizer *passRep) {
insertInstrEnd(blk,newOpcode,passRep,DebugLoc());
} //insertInstrEnd
static void insertInstrEnd(MachineBasicBlock *blk, int newOpcode,
AMDILCFGStructurizer *passRep, DebugLoc DL) {
AMDGPUCFGStructurizer *passRep, DebugLoc DL) {
const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
MachineInstr *newInstr = blk->getParent()
->CreateMachineInstr(tii->get(newOpcode), DL);
@ -3012,7 +3012,7 @@ struct CFGStructTraits<AMDILCFGStructurizer>
static MachineInstr *insertInstrBefore(MachineBasicBlock::iterator instrPos,
int newOpcode,
AMDILCFGStructurizer *passRep) {
AMDGPUCFGStructurizer *passRep) {
MachineInstr *oldInstr = &(*instrPos);
const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
MachineBasicBlock *blk = oldInstr->getParent();
@ -3029,7 +3029,7 @@ struct CFGStructTraits<AMDILCFGStructurizer>
static void insertCondBranchBefore(MachineBasicBlock::iterator instrPos,
int newOpcode,
AMDILCFGStructurizer *passRep,
AMDGPUCFGStructurizer *passRep,
DebugLoc DL) {
MachineInstr *oldInstr = &(*instrPos);
const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
@ -3049,7 +3049,7 @@ struct CFGStructTraits<AMDILCFGStructurizer>
static void insertCondBranchBefore(MachineBasicBlock *blk,
MachineBasicBlock::iterator insertPos,
int newOpcode,
AMDILCFGStructurizer *passRep,
AMDGPUCFGStructurizer *passRep,
RegiT regNum,
DebugLoc DL) {
const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
@ -3066,7 +3066,7 @@ struct CFGStructTraits<AMDILCFGStructurizer>
static void insertCondBranchEnd(MachineBasicBlock *blk,
int newOpcode,
AMDILCFGStructurizer *passRep,
AMDGPUCFGStructurizer *passRep,
RegiT regNum) {
const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
MachineInstr *newInstr =
@ -3080,7 +3080,7 @@ struct CFGStructTraits<AMDILCFGStructurizer>
static void insertAssignInstrBefore(MachineBasicBlock::iterator instrPos,
AMDILCFGStructurizer *passRep,
AMDGPUCFGStructurizer *passRep,
RegiT regNum, int regVal) {
MachineInstr *oldInstr = &(*instrPos);
const AMDGPUInstrInfo *tii =
@ -3094,7 +3094,7 @@ struct CFGStructTraits<AMDILCFGStructurizer>
} //insertAssignInstrBefore
static void insertAssignInstrBefore(MachineBasicBlock *blk,
AMDILCFGStructurizer *passRep,
AMDGPUCFGStructurizer *passRep,
RegiT regNum, int regVal) {
const AMDGPUInstrInfo *tii =
static_cast<const AMDGPUInstrInfo *>(passRep->getTargetInstrInfo());
@ -3113,7 +3113,7 @@ struct CFGStructTraits<AMDILCFGStructurizer>
static void insertCompareInstrBefore(MachineBasicBlock *blk,
MachineBasicBlock::iterator instrPos,
AMDILCFGStructurizer *passRep,
AMDGPUCFGStructurizer *passRep,
RegiT dstReg, RegiT src1Reg,
RegiT src2Reg) {
const AMDGPUInstrInfo *tii =
@ -3153,7 +3153,7 @@ struct CFGStructTraits<AMDILCFGStructurizer>
}
//MachineBasicBlock::ReplaceUsesOfBlockWith doesn't serve the purpose because
//the AMDIL instruction is not recognized as terminator fix this and retire
//the AMDGPU instruction is not recognized as terminator fix this and retire
//this routine
static void replaceInstrUseOfBlockWith(MachineBasicBlock *srcBlk,
MachineBasicBlock *oldBlk,
@ -3196,41 +3196,41 @@ struct CFGStructTraits<AMDILCFGStructurizer>
} //wrapup
static MachineDominatorTree *getDominatorTree(AMDILCFGStructurizer &pass) {
static MachineDominatorTree *getDominatorTree(AMDGPUCFGStructurizer &pass) {
return &pass.getAnalysis<MachineDominatorTree>();
}
static MachinePostDominatorTree*
getPostDominatorTree(AMDILCFGStructurizer &pass) {
getPostDominatorTree(AMDGPUCFGStructurizer &pass) {
return &pass.getAnalysis<MachinePostDominatorTree>();
}
static MachineLoopInfo *getLoopInfo(AMDILCFGStructurizer &pass) {
static MachineLoopInfo *getLoopInfo(AMDGPUCFGStructurizer &pass) {
return &pass.getAnalysis<MachineLoopInfo>();
}
}; // template class CFGStructTraits
} //end of namespace llvm
// createAMDILCFGPreparationPass- Returns a pass
FunctionPass *llvm::createAMDILCFGPreparationPass(TargetMachine &tm
// createAMDGPUCFGPreparationPass- Returns a pass
FunctionPass *llvm::createAMDGPUCFGPreparationPass(TargetMachine &tm
AMDIL_OPT_LEVEL_DECL) {
return new AMDILCFGPrepare(tm AMDIL_OPT_LEVEL_VAR);
return new AMDGPUCFGPrepare(tm AMDIL_OPT_LEVEL_VAR);
}
bool AMDILCFGPrepare::runOnMachineFunction(MachineFunction &func) {
return llvmCFGStruct::CFGStructurizer<AMDILCFGStructurizer>().prepare(func,
bool AMDGPUCFGPrepare::runOnMachineFunction(MachineFunction &func) {
return llvmCFGStruct::CFGStructurizer<AMDGPUCFGStructurizer>().prepare(func,
*this,
TRI);
}
// createAMDILCFGStructurizerPass- Returns a pass
FunctionPass *llvm::createAMDILCFGStructurizerPass(TargetMachine &tm
// createAMDGPUCFGStructurizerPass- Returns a pass
FunctionPass *llvm::createAMDGPUCFGStructurizerPass(TargetMachine &tm
AMDIL_OPT_LEVEL_DECL) {
return new AMDILCFGPerform(tm AMDIL_OPT_LEVEL_VAR);
return new AMDGPUCFGPerform(tm AMDIL_OPT_LEVEL_VAR);
}
bool AMDILCFGPerform::runOnMachineFunction(MachineFunction &func) {
return llvmCFGStruct::CFGStructurizer<AMDILCFGStructurizer>().run(func,
bool AMDGPUCFGPerform::runOnMachineFunction(MachineFunction &func) {
return llvmCFGStruct::CFGStructurizer<AMDGPUCFGStructurizer>().run(func,
*this,
TRI);
}

86
src/gallium/drivers/radeon/AMDILDevice.cpp
View file

@ -11,122 +11,122 @@
using namespace llvm;
// Default implementation for all of the classes.
AMDILDevice::AMDILDevice(AMDGPUSubtarget *ST) : mSTM(ST)
AMDGPUDevice::AMDGPUDevice(AMDGPUSubtarget *ST) : mSTM(ST)
{
mHWBits.resize(AMDILDeviceInfo::MaxNumberCapabilities);
mSWBits.resize(AMDILDeviceInfo::MaxNumberCapabilities);
mHWBits.resize(AMDGPUDeviceInfo::MaxNumberCapabilities);
mSWBits.resize(AMDGPUDeviceInfo::MaxNumberCapabilities);
setCaps();
mDeviceFlag = OCL_DEVICE_ALL;
}
AMDILDevice::~AMDILDevice()
AMDGPUDevice::~AMDGPUDevice()
{
mHWBits.clear();
mSWBits.clear();
}
size_t AMDILDevice::getMaxGDSSize() const
size_t AMDGPUDevice::getMaxGDSSize() const
{
return 0;
}
uint32_t
AMDILDevice::getDeviceFlag() const
AMDGPUDevice::getDeviceFlag() const
{
return mDeviceFlag;
}
size_t AMDILDevice::getMaxNumCBs() const
size_t AMDGPUDevice::getMaxNumCBs() const
{
if (usesHardware(AMDILDeviceInfo::ConstantMem)) {
if (usesHardware(AMDGPUDeviceInfo::ConstantMem)) {
return HW_MAX_NUM_CB;
}
return 0;
}
size_t AMDILDevice::getMaxCBSize() const
size_t AMDGPUDevice::getMaxCBSize() const
{
if (usesHardware(AMDILDeviceInfo::ConstantMem)) {
if (usesHardware(AMDGPUDeviceInfo::ConstantMem)) {
return MAX_CB_SIZE;
}
return 0;
}
size_t AMDILDevice::getMaxScratchSize() const
size_t AMDGPUDevice::getMaxScratchSize() const
{
return 65536;
}
uint32_t AMDILDevice::getStackAlignment() const
uint32_t AMDGPUDevice::getStackAlignment() const
{
return 16;
}
void AMDILDevice::setCaps()
void AMDGPUDevice::setCaps()
{
mSWBits.set(AMDILDeviceInfo::HalfOps);
mSWBits.set(AMDILDeviceInfo::ByteOps);
mSWBits.set(AMDILDeviceInfo::ShortOps);
mSWBits.set(AMDILDeviceInfo::HW64BitDivMod);
if (mSTM->isOverride(AMDILDeviceInfo::NoInline)) {
mSWBits.set(AMDILDeviceInfo::NoInline);
mSWBits.set(AMDGPUDeviceInfo::HalfOps);
mSWBits.set(AMDGPUDeviceInfo::ByteOps);
mSWBits.set(AMDGPUDeviceInfo::ShortOps);
mSWBits.set(AMDGPUDeviceInfo::HW64BitDivMod);
if (mSTM->isOverride(AMDGPUDeviceInfo::NoInline)) {
mSWBits.set(AMDGPUDeviceInfo::NoInline);
}
if (mSTM->isOverride(AMDILDeviceInfo::MacroDB)) {
mSWBits.set(AMDILDeviceInfo::MacroDB);
if (mSTM->isOverride(AMDGPUDeviceInfo::MacroDB)) {
mSWBits.set(AMDGPUDeviceInfo::MacroDB);
}
if (mSTM->isOverride(AMDILDeviceInfo::Debug)) {
mSWBits.set(AMDILDeviceInfo::ConstantMem);
if (mSTM->isOverride(AMDGPUDeviceInfo::Debug)) {
mSWBits.set(AMDGPUDeviceInfo::ConstantMem);
} else {
mHWBits.set(AMDILDeviceInfo::ConstantMem);
mHWBits.set(AMDGPUDeviceInfo::ConstantMem);
}
if (mSTM->isOverride(AMDILDeviceInfo::Debug)) {
mSWBits.set(AMDILDeviceInfo::PrivateMem);
if (mSTM->isOverride(AMDGPUDeviceInfo::Debug)) {
mSWBits.set(AMDGPUDeviceInfo::PrivateMem);
} else {
mHWBits.set(AMDILDeviceInfo::PrivateMem);
mHWBits.set(AMDGPUDeviceInfo::PrivateMem);
}
if (mSTM->isOverride(AMDILDeviceInfo::BarrierDetect)) {
mSWBits.set(AMDILDeviceInfo::BarrierDetect);
if (mSTM->isOverride(AMDGPUDeviceInfo::BarrierDetect)) {
mSWBits.set(AMDGPUDeviceInfo::BarrierDetect);
}
mSWBits.set(AMDILDeviceInfo::ByteLDSOps);
mSWBits.set(AMDILDeviceInfo::LongOps);
mSWBits.set(AMDGPUDeviceInfo::ByteLDSOps);
mSWBits.set(AMDGPUDeviceInfo::LongOps);
}
AMDILDeviceInfo::ExecutionMode
AMDILDevice::getExecutionMode(AMDILDeviceInfo::Caps Caps) const
AMDGPUDeviceInfo::ExecutionMode
AMDGPUDevice::getExecutionMode(AMDGPUDeviceInfo::Caps Caps) const
{
if (mHWBits[Caps]) {
assert(!mSWBits[Caps] && "Cannot set both SW and HW caps");
return AMDILDeviceInfo::Hardware;
return AMDGPUDeviceInfo::Hardware;
}
if (mSWBits[Caps]) {
assert(!mHWBits[Caps] && "Cannot set both SW and HW caps");
return AMDILDeviceInfo::Software;
return AMDGPUDeviceInfo::Software;
}
return AMDILDeviceInfo::Unsupported;
return AMDGPUDeviceInfo::Unsupported;
}
bool AMDILDevice::isSupported(AMDILDeviceInfo::Caps Mode) const
bool AMDGPUDevice::isSupported(AMDGPUDeviceInfo::Caps Mode) const
{
return getExecutionMode(Mode) != AMDILDeviceInfo::Unsupported;
return getExecutionMode(Mode) != AMDGPUDeviceInfo::Unsupported;
}
bool AMDILDevice::usesHardware(AMDILDeviceInfo::Caps Mode) const
bool AMDGPUDevice::usesHardware(AMDGPUDeviceInfo::Caps Mode) const
{
return getExecutionMode(Mode) == AMDILDeviceInfo::Hardware;
return getExecutionMode(Mode) == AMDGPUDeviceInfo::Hardware;
}
bool AMDILDevice::usesSoftware(AMDILDeviceInfo::Caps Mode) const
bool AMDGPUDevice::usesSoftware(AMDGPUDeviceInfo::Caps Mode) const
{
return getExecutionMode(Mode) == AMDILDeviceInfo::Software;
return getExecutionMode(Mode) == AMDGPUDeviceInfo::Software;
}
std::string
AMDILDevice::getDataLayout() const
AMDGPUDevice::getDataLayout() const
{
return std::string("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16"
"-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"

20
src/gallium/drivers/radeon/AMDILDevice.h
View file

@ -21,17 +21,17 @@
namespace llvm {
class AMDGPUSubtarget;
class AMDILAsmPrinter;
class AMDILPointerManager;
class AMDGPUAsmPrinter;
class AMDGPUPointerManager;
class AsmPrinter;
class MCStreamer;
//===----------------------------------------------------------------------===//
// Interface for data that is specific to a single device
//===----------------------------------------------------------------------===//
class AMDILDevice {
class AMDGPUDevice {
public:
AMDILDevice(AMDGPUSubtarget *ST);
virtual ~AMDILDevice();
AMDGPUDevice(AMDGPUSubtarget *ST);
virtual ~AMDGPUDevice();
// Enum values for the various memory types.
enum {
@ -98,9 +98,9 @@ public:
// software that emulates it with possibly using the hardware for
// support since the hardware does not fully comply with OpenCL
// specs.
bool isSupported(AMDILDeviceInfo::Caps Mode) const;
bool usesHardware(AMDILDeviceInfo::Caps Mode) const;
bool usesSoftware(AMDILDeviceInfo::Caps Mode) const;
bool isSupported(AMDGPUDeviceInfo::Caps Mode) const;
bool usesHardware(AMDGPUDeviceInfo::Caps Mode) const;
bool usesSoftware(AMDGPUDeviceInfo::Caps Mode) const;
virtual std::string getDataLayout() const;
static const unsigned int MAX_LDS_SIZE_700 = 16384;
static const unsigned int MAX_LDS_SIZE_800 = 32768;
@ -114,8 +114,8 @@ protected:
AMDGPUSubtarget *mSTM;
uint32_t mDeviceFlag;
private:
AMDILDeviceInfo::ExecutionMode
getExecutionMode(AMDILDeviceInfo::Caps Caps) const;
AMDGPUDeviceInfo::ExecutionMode
getExecutionMode(AMDGPUDeviceInfo::Caps Caps) const;
}; // AMDILDevice
} // namespace llvm

30
src/gallium/drivers/radeon/AMDILDeviceInfo.cpp
View file

@ -15,19 +15,19 @@
using namespace llvm;
namespace llvm {
namespace AMDILDeviceInfo {
AMDILDevice*
namespace AMDGPUDeviceInfo {
AMDGPUDevice*
getDeviceFromName(const std::string &deviceName, AMDGPUSubtarget *ptr,
bool is64bit, bool is64on32bit)
{
if (deviceName.c_str()[2] == '7') {
switch (deviceName.c_str()[3]) {
case '1':
return new AMDIL710Device(ptr);
return new AMDGPU710Device(ptr);
case '7':
return new AMDIL770Device(ptr);
return new AMDGPU770Device(ptr);
default:
return new AMDIL7XXDevice(ptr);
return new AMDGPU7XXDevice(ptr);
};
} else if (deviceName == "cypress") {
#if DEBUG
@ -35,28 +35,28 @@ getDeviceFromName(const std::string &deviceName, AMDGPUSubtarget *ptr,
assert(!is64on32bit && "This device does not support 64bit"
" on 32bit pointers!");
#endif
return new AMDILCypressDevice(ptr);
return new AMDGPUCypressDevice(ptr);
} else if (deviceName == "juniper") {
#if DEBUG
assert(!is64bit && "This device does not support 64bit pointers!");
assert(!is64on32bit && "This device does not support 64bit"
" on 32bit pointers!");
#endif
return new AMDILEvergreenDevice(ptr);
return new AMDGPUEvergreenDevice(ptr);
} else if (deviceName == "redwood") {
#if DEBUG
assert(!is64bit && "This device does not support 64bit pointers!");
assert(!is64on32bit && "This device does not support 64bit"
" on 32bit pointers!");
#endif
return new AMDILRedwoodDevice(ptr);
return new AMDGPURedwoodDevice(ptr);
} else if (deviceName == "cedar") {
#if DEBUG
assert(!is64bit && "This device does not support 64bit pointers!");
assert(!is64on32bit && "This device does not support 64bit"
" on 32bit pointers!");
#endif
return new AMDILCedarDevice(ptr);
return new AMDGPUCedarDevice(ptr);
} else if (deviceName == "barts"
|| deviceName == "turks") {
#if DEBUG
@ -64,31 +64,31 @@ getDeviceFromName(const std::string &deviceName, AMDGPUSubtarget *ptr,
assert(!is64on32bit && "This device does not support 64bit"
" on 32bit pointers!");
#endif
return new AMDILNIDevice(ptr);
return new AMDGPUNIDevice(ptr);
} else if (deviceName == "cayman") {
#if DEBUG
assert(!is64bit && "This device does not support 64bit pointers!");
assert(!is64on32bit && "This device does not support 64bit"
" on 32bit pointers!");
#endif
return new AMDILCaymanDevice(ptr);
return new AMDGPUCaymanDevice(ptr);
} else if (deviceName == "caicos") {
#if DEBUG
assert(!is64bit && "This device does not support 64bit pointers!");
assert(!is64on32bit && "This device does not support 64bit"
" on 32bit pointers!");
#endif
return new AMDILNIDevice(ptr);
return new AMDGPUNIDevice(ptr);
} else if (deviceName == "SI") {
return new AMDILSIDevice(ptr);
return new AMDGPUSIDevice(ptr);
} else {
#if DEBUG
assert(!is64bit && "This device does not support 64bit pointers!");
assert(!is64on32bit && "This device does not support 64bit"
" on 32bit pointers!");
#endif
return new AMDIL7XXDevice(ptr);
return new AMDGPU7XXDevice(ptr);
}
}
} // End namespace AMDILDeviceInfo
} // End namespace AMDGPUDeviceInfo
} // End namespace llvm

6
src/gallium/drivers/radeon/AMDILDeviceInfo.h
View file

@ -14,9 +14,9 @@
namespace llvm
{
class AMDILDevice;
class AMDGPUDevice;
class AMDGPUSubtarget;
namespace AMDILDeviceInfo
namespace AMDGPUDeviceInfo
{
// Each Capabilities can be executed using a hardware instruction,
// emulated with a sequence of software instructions, or not
@ -82,7 +82,7 @@ namespace llvm
};
AMDILDevice*
AMDGPUDevice*
getDeviceFromName(const std::string &name, AMDGPUSubtarget *ptr,
bool is64bit = false, bool is64on32bit = false);
} // namespace AMDILDeviceInfo

128
src/gallium/drivers/radeon/AMDILEvergreenDevice.cpp
View file

@ -13,8 +13,8 @@
using namespace llvm;
AMDILEvergreenDevice::AMDILEvergreenDevice(AMDGPUSubtarget *ST)
: AMDILDevice(ST) {
AMDGPUEvergreenDevice::AMDGPUEvergreenDevice(AMDGPUSubtarget *ST)
: AMDGPUDevice(ST) {
setCaps();
std::string name = ST->getDeviceName();
if (name == "cedar") {
@ -28,28 +28,28 @@ AMDILEvergreenDevice::AMDILEvergreenDevice(AMDGPUSubtarget *ST)
}
}
AMDILEvergreenDevice::~AMDILEvergreenDevice() {
AMDGPUEvergreenDevice::~AMDGPUEvergreenDevice() {
}
size_t AMDILEvergreenDevice::getMaxLDSSize() const {
if (usesHardware(AMDILDeviceInfo::LocalMem)) {
size_t AMDGPUEvergreenDevice::getMaxLDSSize() const {
if (usesHardware(AMDGPUDeviceInfo::LocalMem)) {
return MAX_LDS_SIZE_800;
} else {
return 0;
}
}
size_t AMDILEvergreenDevice::getMaxGDSSize() const {
if (usesHardware(AMDILDeviceInfo::RegionMem)) {
size_t AMDGPUEvergreenDevice::getMaxGDSSize() const {
if (usesHardware(AMDGPUDeviceInfo::RegionMem)) {
return MAX_LDS_SIZE_800;
} else {
return 0;
}
}
uint32_t AMDILEvergreenDevice::getMaxNumUAVs() const {
uint32_t AMDGPUEvergreenDevice::getMaxNumUAVs() const {
return 12;
}
uint32_t AMDILEvergreenDevice::getResourceID(uint32_t id) const {
uint32_t AMDGPUEvergreenDevice::getResourceID(uint32_t id) const {
switch(id) {
default:
assert(0 && "ID type passed in is unknown!");
@ -61,19 +61,19 @@ uint32_t AMDILEvergreenDevice::getResourceID(uint32_t id) const {
case ARENA_UAV_ID:
return DEFAULT_ARENA_UAV_ID;
case LDS_ID:
if (usesHardware(AMDILDeviceInfo::LocalMem)) {
if (usesHardware(AMDGPUDeviceInfo::LocalMem)) {
return DEFAULT_LDS_ID;
} else {
return DEFAULT_ARENA_UAV_ID;
}
case GDS_ID:
if (usesHardware(AMDILDeviceInfo::RegionMem)) {
if (usesHardware(AMDGPUDeviceInfo::RegionMem)) {
return DEFAULT_GDS_ID;
} else {
return DEFAULT_ARENA_UAV_ID;
}
case SCRATCH_ID:
if (usesHardware(AMDILDeviceInfo::PrivateMem)) {
if (usesHardware(AMDGPUDeviceInfo::PrivateMem)) {
return DEFAULT_SCRATCH_ID;
} else {
return DEFAULT_ARENA_UAV_ID;
@ -82,101 +82,101 @@ uint32_t AMDILEvergreenDevice::getResourceID(uint32_t id) const {
return 0;
}
size_t AMDILEvergreenDevice::getWavefrontSize() const {
return AMDILDevice::WavefrontSize;
size_t AMDGPUEvergreenDevice::getWavefrontSize() const {
return AMDGPUDevice::WavefrontSize;
}
uint32_t AMDILEvergreenDevice::getGeneration() const {
return AMDILDeviceInfo::HD5XXX;
uint32_t AMDGPUEvergreenDevice::getGeneration() const {
return AMDGPUDeviceInfo::HD5XXX;
}
void AMDILEvergreenDevice::setCaps() {
mSWBits.set(AMDILDeviceInfo::ArenaSegment);
mHWBits.set(AMDILDeviceInfo::ArenaUAV);
mHWBits.set(AMDILDeviceInfo::HW64BitDivMod);
mSWBits.reset(AMDILDeviceInfo::HW64BitDivMod);
mSWBits.set(AMDILDeviceInfo::Signed24BitOps);
if (mSTM->isOverride(AMDILDeviceInfo::ByteStores)) {
mHWBits.set(AMDILDeviceInfo::ByteStores);
void AMDGPUEvergreenDevice::setCaps() {
mSWBits.set(AMDGPUDeviceInfo::ArenaSegment);
mHWBits.set(AMDGPUDeviceInfo::ArenaUAV);
mHWBits.set(AMDGPUDeviceInfo::HW64BitDivMod);
mSWBits.reset(AMDGPUDeviceInfo::HW64BitDivMod);
mSWBits.set(AMDGPUDeviceInfo::Signed24BitOps);
if (mSTM->isOverride(AMDGPUDeviceInfo::ByteStores)) {
mHWBits.set(AMDGPUDeviceInfo::ByteStores);
}
if (mSTM->isOverride(AMDILDeviceInfo::Debug)) {
mSWBits.set(AMDILDeviceInfo::LocalMem);
mSWBits.set(AMDILDeviceInfo::RegionMem);
if (mSTM->isOverride(AMDGPUDeviceInfo::Debug)) {
mSWBits.set(AMDGPUDeviceInfo::LocalMem);
mSWBits.set(AMDGPUDeviceInfo::RegionMem);
} else {
mHWBits.set(AMDILDeviceInfo::LocalMem);
mHWBits.set(AMDILDeviceInfo::RegionMem);
mHWBits.set(AMDGPUDeviceInfo::LocalMem);
mHWBits.set(AMDGPUDeviceInfo::RegionMem);
}
mHWBits.set(AMDILDeviceInfo::Images);
if (mSTM->isOverride(AMDILDeviceInfo::NoAlias)) {
mHWBits.set(AMDILDeviceInfo::NoAlias);
mHWBits.set(AMDGPUDeviceInfo::Images);
if (mSTM->isOverride(AMDGPUDeviceInfo::NoAlias)) {
mHWBits.set(AMDGPUDeviceInfo::NoAlias);
}
mHWBits.set(AMDILDeviceInfo::CachedMem);
if (mSTM->isOverride(AMDILDeviceInfo::MultiUAV)) {
mHWBits.set(AMDILDeviceInfo::MultiUAV);
mHWBits.set(AMDGPUDeviceInfo::CachedMem);
if (mSTM->isOverride(AMDGPUDeviceInfo::MultiUAV)) {
mHWBits.set(AMDGPUDeviceInfo::MultiUAV);
}
mHWBits.set(AMDILDeviceInfo::ByteLDSOps);
mSWBits.reset(AMDILDeviceInfo::ByteLDSOps);
mHWBits.set(AMDILDeviceInfo::ArenaVectors);
mHWBits.set(AMDILDeviceInfo::LongOps);
mSWBits.reset(AMDILDeviceInfo::LongOps);
mHWBits.set(AMDILDeviceInfo::TmrReg);
mHWBits.set(AMDGPUDeviceInfo::ByteLDSOps);
mSWBits.reset(AMDGPUDeviceInfo::ByteLDSOps);
mHWBits.set(AMDGPUDeviceInfo::ArenaVectors);
mHWBits.set(AMDGPUDeviceInfo::LongOps);
mSWBits.reset(AMDGPUDeviceInfo::LongOps);
mHWBits.set(AMDGPUDeviceInfo::TmrReg);
}
AsmPrinter*
AMDILEvergreenDevice::getAsmPrinter(TargetMachine& TM, MCStreamer &Streamer) const
AMDGPUEvergreenDevice::getAsmPrinter(TargetMachine& TM, MCStreamer &Streamer) const
{
#ifdef UPSTREAM_LLVM
return new AMDILEGAsmPrinter(TM, Streamer);
return new AMDGPUEGAsmPrinter(TM, Streamer);
#else
return NULL;
#endif
}
AMDILCypressDevice::AMDILCypressDevice(AMDGPUSubtarget *ST)
: AMDILEvergreenDevice(ST) {
AMDGPUCypressDevice::AMDGPUCypressDevice(AMDGPUSubtarget *ST)
: AMDGPUEvergreenDevice(ST) {
setCaps();
}
AMDILCypressDevice::~AMDILCypressDevice() {
AMDGPUCypressDevice::~AMDGPUCypressDevice() {
}
void AMDILCypressDevice::setCaps() {
if (mSTM->isOverride(AMDILDeviceInfo::DoubleOps)) {
mHWBits.set(AMDILDeviceInfo::DoubleOps);
mHWBits.set(AMDILDeviceInfo::FMA);
void AMDGPUCypressDevice::setCaps() {
if (mSTM->isOverride(AMDGPUDeviceInfo::DoubleOps)) {
mHWBits.set(AMDGPUDeviceInfo::DoubleOps);
mHWBits.set(AMDGPUDeviceInfo::FMA);
}
}
AMDILCedarDevice::AMDILCedarDevice(AMDGPUSubtarget *ST)
: AMDILEvergreenDevice(ST) {
AMDGPUCedarDevice::AMDGPUCedarDevice(AMDGPUSubtarget *ST)
: AMDGPUEvergreenDevice(ST) {
setCaps();
}
AMDILCedarDevice::~AMDILCedarDevice() {
AMDGPUCedarDevice::~AMDGPUCedarDevice() {
}
void AMDILCedarDevice::setCaps() {
mSWBits.set(AMDILDeviceInfo::FMA);
void AMDGPUCedarDevice::setCaps() {
mSWBits.set(AMDGPUDeviceInfo::FMA);
}
size_t AMDILCedarDevice::getWavefrontSize() const {
return AMDILDevice::QuarterWavefrontSize;
size_t AMDGPUCedarDevice::getWavefrontSize() const {
return AMDGPUDevice::QuarterWavefrontSize;
}
AMDILRedwoodDevice::AMDILRedwoodDevice(AMDGPUSubtarget *ST)
: AMDILEvergreenDevice(ST) {
AMDGPURedwoodDevice::AMDGPURedwoodDevice(AMDGPUSubtarget *ST)
: AMDGPUEvergreenDevice(ST) {
setCaps();
}
AMDILRedwoodDevice::~AMDILRedwoodDevice()
AMDGPURedwoodDevice::~AMDGPURedwoodDevice()
{
}
void AMDILRedwoodDevice::setCaps() {
mSWBits.set(AMDILDeviceInfo::FMA);
void AMDGPURedwoodDevice::setCaps() {
mSWBits.set(AMDGPUDeviceInfo::FMA);
}
size_t AMDILRedwoodDevice::getWavefrontSize() const {
return AMDILDevice::HalfWavefrontSize;
size_t AMDGPURedwoodDevice::getWavefrontSize() const {
return AMDGPUDevice::HalfWavefrontSize;
}

46
src/gallium/drivers/radeon/AMDILEvergreenDevice.h
View file

@ -26,14 +26,14 @@ namespace llvm {
//===----------------------------------------------------------------------===//
// The AMDILEvergreenDevice is the base device class for all of the Evergreen
// The AMDGPUEvergreenDevice is the base device class for all of the Evergreen
// series of cards. This class contains information required to differentiate
// the Evergreen device from the generic AMDILDevice. This device represents
// the Evergreen device from the generic AMDGPUDevice. This device represents
// that capabilities of the 'Juniper' cards, also known as the HD57XX.
class AMDILEvergreenDevice : public AMDILDevice {
class AMDGPUEvergreenDevice : public AMDGPUDevice {
public:
AMDILEvergreenDevice(AMDGPUSubtarget *ST);
virtual ~AMDILEvergreenDevice();
AMDGPUEvergreenDevice(AMDGPUSubtarget *ST);
virtual ~AMDGPUEvergreenDevice();
virtual size_t getMaxLDSSize() const;
virtual size_t getMaxGDSSize() const;
virtual size_t getWavefrontSize() const;
@ -44,46 +44,46 @@ public:
getAsmPrinter(TargetMachine& TM, MCStreamer &Streamer) const;
protected:
virtual void setCaps();
}; // AMDILEvergreenDevice
}; // AMDGPUEvergreenDevice
// The AMDILCypressDevice is similiar to the AMDILEvergreenDevice, except it has
// The AMDGPUCypressDevice is similiar to the AMDGPUEvergreenDevice, except it has
// support for double precision operations. This device is used to represent
// both the Cypress and Hemlock cards, which are commercially known as HD58XX
// and HD59XX cards.
class AMDILCypressDevice : public AMDILEvergreenDevice {
class AMDGPUCypressDevice : public AMDGPUEvergreenDevice {
public:
AMDILCypressDevice(AMDGPUSubtarget *ST);
virtual ~AMDILCypressDevice();
AMDGPUCypressDevice(AMDGPUSubtarget *ST);
virtual ~AMDGPUCypressDevice();
private:
virtual void setCaps();
}; // AMDILCypressDevice
}; // AMDGPUCypressDevice
// The AMDILCedarDevice is the class that represents all of the 'Cedar' based
// devices. This class differs from the base AMDILEvergreenDevice in that the
// The AMDGPUCedarDevice is the class that represents all of the 'Cedar' based
// devices. This class differs from the base AMDGPUEvergreenDevice in that the
// device is a ~quarter of the 'Juniper'. These are commercially known as the
// HD54XX and HD53XX series of cards.
class AMDILCedarDevice : public AMDILEvergreenDevice {
class AMDGPUCedarDevice : public AMDGPUEvergreenDevice {
public:
AMDILCedarDevice(AMDGPUSubtarget *ST);
virtual ~AMDILCedarDevice();
AMDGPUCedarDevice(AMDGPUSubtarget *ST);
virtual ~AMDGPUCedarDevice();
virtual size_t getWavefrontSize() const;
private:
virtual void setCaps();
}; // AMDILCedarDevice
}; // AMDGPUCedarDevice
// The AMDILRedwoodDevice is the class the represents all of the 'Redwood' based
// The AMDGPURedwoodDevice is the class the represents all of the 'Redwood' based
// devices. This class differs from the base class, in that these devices are
// considered about half of a 'Juniper' device. These are commercially known as
// the HD55XX and HD56XX series of cards.
class AMDILRedwoodDevice : public AMDILEvergreenDevice {
class AMDGPURedwoodDevice : public AMDGPUEvergreenDevice {
public:
AMDILRedwoodDevice(AMDGPUSubtarget *ST);
virtual ~AMDILRedwoodDevice();
AMDGPURedwoodDevice(AMDGPUSubtarget *ST);
virtual ~AMDGPURedwoodDevice();
virtual size_t getWavefrontSize() const;
private:
virtual void setCaps();
}; // AMDILRedwoodDevice
}; // AMDGPURedwoodDevice
} // namespace llvm
#endif // _AMDILEVERGREENDEVICE_H_
#endif // _AMDGPUEVERGREENDEVICE_H_

14
src/gallium/drivers/radeon/AMDILFrameLowering.cpp
View file

@ -14,40 +14,40 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
using namespace llvm;
AMDILFrameLowering::AMDILFrameLowering(StackDirection D, unsigned StackAl,
AMDGPUFrameLowering::AMDGPUFrameLowering(StackDirection D, unsigned StackAl,
int LAO, unsigned TransAl)
: TargetFrameLowering(D, StackAl, LAO, TransAl)
{
}
AMDILFrameLowering::~AMDILFrameLowering()
AMDGPUFrameLowering::~AMDGPUFrameLowering()
{
}
/// getFrameIndexOffset - Returns the displacement from the frame register to
/// the stack frame of the specified index.
int AMDILFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
int AMDGPUFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
int FI) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return MFI->getObjectOffset(FI);
}
const TargetFrameLowering::SpillSlot *
AMDILFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const
AMDGPUFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const
{
NumEntries = 0;
return 0;
}
void
AMDILFrameLowering::emitPrologue(MachineFunction &MF) const
AMDGPUFrameLowering::emitPrologue(MachineFunction &MF) const
{
}
void
AMDILFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
AMDGPUFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
{
}
bool
AMDILFrameLowering::hasFP(const MachineFunction &MF) const
AMDGPUFrameLowering::hasFP(const MachineFunction &MF) const
{
return false;
}

10
src/gallium/drivers/radeon/AMDILFrameLowering.h
View file

@ -23,17 +23,17 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetFrameLowering.h"
/// Information about the stack frame layout on the AMDIL targets. It holds
/// Information about the stack frame layout on the AMDGPU targets. It holds
/// the direction of the stack growth, the known stack alignment on entry to
/// each function, and the offset to the locals area.
/// See TargetFrameInfo for more comments.
namespace llvm {
class AMDILFrameLowering : public TargetFrameLowering {
class AMDGPUFrameLowering : public TargetFrameLowering {
public:
AMDILFrameLowering(StackDirection D, unsigned StackAl, int LAO, unsigned
AMDGPUFrameLowering(StackDirection D, unsigned StackAl, int LAO, unsigned
TransAl = 1);
virtual ~AMDILFrameLowering();
virtual ~AMDGPUFrameLowering();
virtual int getFrameIndexOffset(const MachineFunction &MF,
int FI) const;
virtual const SpillSlot *
@ -41,6 +41,6 @@ namespace llvm {
virtual void emitPrologue(MachineFunction &MF) const;
virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
virtual bool hasFP(const MachineFunction &MF) const;
}; // class AMDILFrameLowering
}; // class AMDGPUFrameLowering
} // namespace llvm
#endif // _AMDILFRAME_LOWERING_H_

102
src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp
View file

@ -29,17 +29,17 @@ using namespace llvm;
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// AMDILDAGToDAGISel - AMDIL specific code to select AMDIL machine instructions
// AMDGPUDAGToDAGISel - AMDGPU specific code to select AMDGPU machine instructions
// //for SelectionDAG operations.
//
namespace {
class AMDILDAGToDAGISel : public SelectionDAGISel {
// Subtarget - Keep a pointer to the AMDIL Subtarget around so that we can
class AMDGPUDAGToDAGISel : public SelectionDAGISel {
// Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
// make the right decision when generating code for different targets.
const AMDGPUSubtarget &Subtarget;
public:
AMDILDAGToDAGISel(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
virtual ~AMDILDAGToDAGISel();
AMDGPUDAGToDAGISel(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
virtual ~AMDGPUDAGToDAGISel();
SDNode *Select(SDNode *N);
virtual const char *getPassName() const;
@ -76,28 +76,28 @@ private:
};
} // end anonymous namespace
// createAMDILISelDag - This pass converts a legalized DAG into a AMDIL-specific
// createAMDGPUISelDag - This pass converts a legalized DAG into a AMDGPU-specific
// DAG, ready for instruction scheduling.
//
FunctionPass *llvm::createAMDILISelDag(TargetMachine &TM
FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
AMDIL_OPT_LEVEL_DECL) {
return new AMDILDAGToDAGISel(TM AMDIL_OPT_LEVEL_VAR);
return new AMDGPUDAGToDAGISel(TM AMDIL_OPT_LEVEL_VAR);
}
AMDILDAGToDAGISel::AMDILDAGToDAGISel(TargetMachine &TM
AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM
AMDIL_OPT_LEVEL_DECL)
: SelectionDAGISel(TM AMDIL_OPT_LEVEL_VAR), Subtarget(TM.getSubtarget<AMDGPUSubtarget>())
{
}
AMDILDAGToDAGISel::~AMDILDAGToDAGISel() {
AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
}
SDValue AMDILDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
bool AMDILDAGToDAGISel::SelectADDRParam(
bool AMDGPUDAGToDAGISel::SelectADDRParam(
SDValue Addr, SDValue& R1, SDValue& R2) {
if (Addr.getOpcode() == ISD::FrameIndex) {
@ -118,7 +118,7 @@ bool AMDILDAGToDAGISel::SelectADDRParam(
return true;
}
bool AMDILDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress) {
return false;
@ -127,7 +127,7 @@ bool AMDILDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
}
bool AMDILDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress) {
return false;
@ -151,7 +151,7 @@ bool AMDILDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
return true;
}
SDNode *AMDILDAGToDAGISel::Select(SDNode *N) {
SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
unsigned int Opc = N->getOpcode();
if (N->isMachineOpcode()) {
return NULL; // Already selected.
@ -173,7 +173,7 @@ SDNode *AMDILDAGToDAGISel::Select(SDNode *N) {
return SelectCode(N);
}
bool AMDILDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
if (!ptr) {
return false;
}
@ -181,7 +181,7 @@ bool AMDILDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
}
const Value * AMDILDAGToDAGISel::getBasePointerValue(const Value *V)
const Value * AMDGPUDAGToDAGISel::getBasePointerValue(const Value *V)
{
if (!V) {
return NULL;
@ -222,26 +222,26 @@ const Value * AMDILDAGToDAGISel::getBasePointerValue(const Value *V)
return ret;
}
bool AMDILDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
return checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS);
bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
}
bool AMDILDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
return (!checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS)
&& !checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS)
&& !checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS));
bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
&& !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
&& !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
}
bool AMDILDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
return checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS);
bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
}
bool AMDILDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
return checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS);
bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
}
bool AMDILDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
if (checkType(N->getSrcValue(), AMDILAS::CONSTANT_ADDRESS)) {
bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
if (checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)) {
return true;
}
MachineMemOperand *MMO = N->getMemOperand();
@ -252,27 +252,27 @@ bool AMDILDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
&& ((V && dyn_cast<GlobalValue>(V))
|| (BV && dyn_cast<GlobalValue>(
getBasePointerValue(MMO->getValue()))))) {
return checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS);
return checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS);
} else {
return false;
}
}
bool AMDILDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
return checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS);
bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
}
bool AMDILDAGToDAGISel::isLocalLoad(const LoadSDNode *N) {
return checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS);
bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) {
return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
}
bool AMDILDAGToDAGISel::isRegionLoad(const LoadSDNode *N) {
return checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS);
bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) {
return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
}
bool AMDILDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
MachineMemOperand *MMO = N->getMemOperand();
if (checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS)) {
if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
if (MMO) {
const Value *V = MMO->getValue();
const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
@ -284,28 +284,28 @@ bool AMDILDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
return false;
}
bool AMDILDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
if (checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS)) {
bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
// Check to make sure we are not a constant pool load or a constant load
// that is marked as a private load
if (isCPLoad(N) || isConstantLoad(N, -1)) {
return false;
}
}
if (!checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS)
&& !checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS)
&& !checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS)
&& !checkType(N->getSrcValue(), AMDILAS::CONSTANT_ADDRESS)
&& !checkType(N->getSrcValue(), AMDILAS::PARAM_D_ADDRESS)
&& !checkType(N->getSrcValue(), AMDILAS::PARAM_I_ADDRESS))
if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
&& !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
&& !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
&& !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
&& !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
&& !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS))
{
return true;
}
return false;
}
const char *AMDILDAGToDAGISel::getPassName() const {
return "AMDIL DAG->DAG Pattern Instruction Selection";
const char *AMDGPUDAGToDAGISel::getPassName() const {
return "AMDGPU DAG->DAG Pattern Instruction Selection";
}
#ifdef DEBUGTMP
@ -315,7 +315,7 @@ const char *AMDILDAGToDAGISel::getPassName() const {
///==== AMDGPU Functions ====///
bool AMDILDAGToDAGISel::SelectADDR8BitOffset(SDValue Addr, SDValue& Base,
bool AMDGPUDAGToDAGISel::SelectADDR8BitOffset(SDValue Addr, SDValue& Base,
SDValue& Offset) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress) {
@ -352,7 +352,7 @@ bool AMDILDAGToDAGISel::SelectADDR8BitOffset(SDValue Addr, SDValue& Base,
return true;
}
bool AMDILDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
SDValue &Offset)
{
ConstantSDNode * IMMOffset;
@ -380,7 +380,7 @@ bool AMDILDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
return true;
}
bool AMDILDAGToDAGISel::SelectADDRReg(SDValue Addr, SDValue& Base,
bool AMDGPUDAGToDAGISel::SelectADDRReg(SDValue Addr, SDValue& Base,
SDValue& Offset) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress ||

4
src/gallium/drivers/radeon/AMDILISelLowering.cpp
View file

@ -223,7 +223,7 @@ void AMDGPUTargetLowering::InitAMDILLowering()
setOperationAction(ISD::SELECT, VT, Expand);
}
if (STM.device()->isSupported(AMDILDeviceInfo::LongOps)) {
if (STM.device()->isSupported(AMDGPUDeviceInfo::LongOps)) {
setOperationAction(ISD::MULHU, MVT::i64, Expand);
setOperationAction(ISD::MULHU, MVT::v2i64, Expand);
setOperationAction(ISD::MULHS, MVT::i64, Expand);
@ -237,7 +237,7 @@ void AMDGPUTargetLowering::InitAMDILLowering()
setOperationAction(ISD::ZERO_EXTEND, MVT::v2i64, Expand);
setOperationAction(ISD::ANY_EXTEND, MVT::v2i64, Expand);
}
if (STM.device()->isSupported(AMDILDeviceInfo::DoubleOps)) {
if (STM.device()->isSupported(AMDGPUDeviceInfo::DoubleOps)) {
// we support loading/storing v2f64 but not operations on the type
setOperationAction(ISD::FADD, MVT::v2f64, Expand);
setOperationAction(ISD::FSUB, MVT::v2f64, Expand);

28
src/gallium/drivers/radeon/AMDILInstrInfo.td
View file

@ -14,40 +14,40 @@
// Predicate that is set to true if the hardware supports double precision
// divide
def HasHWDDiv : Predicate<"Subtarget.device()"
"->getGeneration() > AMDILDeviceInfo::HD4XXX && "
"Subtarget.device()->usesHardware(AMDILDeviceInfo::DoubleOps)">;
"->getGeneration() > AMDGPUDeviceInfo::HD4XXX && "
"Subtarget.device()->usesHardware(AMDGPUDeviceInfo::DoubleOps)">;
// Predicate that is set to true if the hardware supports double, but not double
// precision divide in hardware
def HasSWDDiv : Predicate<"Subtarget.device()"
"->getGeneration() == AMDILDeviceInfo::HD4XXX &&"
"Subtarget.device()->usesHardware(AMDILDeviceInfo::DoubleOps)">;
"->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
"Subtarget.device()->usesHardware(AMDGPUDeviceInfo::DoubleOps)">;
// Predicate that is set to true if the hardware support 24bit signed
// math ops. Otherwise a software expansion to 32bit math ops is used instead.
def HasHWSign24Bit : Predicate<"Subtarget.device()"
"->getGeneration() > AMDILDeviceInfo::HD5XXX">;
"->getGeneration() > AMDGPUDeviceInfo::HD5XXX">;
// Predicate that is set to true if 64bit operations are supported or not
def HasHW64Bit : Predicate<"Subtarget.device()"
"->usesHardware(AMDILDeviceInfo::LongOps)">;
"->usesHardware(AMDGPUDeviceInfo::LongOps)">;
def HasSW64Bit : Predicate<"Subtarget.device()"
"->usesSoftware(AMDILDeviceInfo::LongOps)">;
"->usesSoftware(AMDGPUDeviceInfo::LongOps)">;
// Predicate that is set to true if the timer register is supported
def HasTmrRegister : Predicate<"Subtarget.device()"
"->isSupported(AMDILDeviceInfo::TmrReg)">;
"->isSupported(AMDGPUDeviceInfo::TmrReg)">;
// Predicate that is true if we are at least evergreen series
def HasDeviceIDInst : Predicate<"Subtarget.device()"
"->getGeneration() >= AMDILDeviceInfo::HD5XXX">;
"->getGeneration() >= AMDGPUDeviceInfo::HD5XXX">;
// Predicate that is true if we have region address space.
def hasRegionAS : Predicate<"Subtarget.device()"
"->usesHardware(AMDILDeviceInfo::RegionMem)">;
"->usesHardware(AMDGPUDeviceInfo::RegionMem)">;
// Predicate that is false if we don't have region address space.
def noRegionAS : Predicate<"!Subtarget.device()"
"->isSupported(AMDILDeviceInfo::RegionMem)">;
"->isSupported(AMDGPUDeviceInfo::RegionMem)">;
// Predicate that is set to true if 64bit Mul is supported in the IL or not
@ -55,14 +55,14 @@ def HasHW64Mul : Predicate<"Subtarget.calVersion()"
">= CAL_VERSION_SC_139"
"&& Subtarget.device()"
"->getGeneration() >="
"AMDILDeviceInfo::HD5XXX">;
"AMDGPUDeviceInfo::HD5XXX">;
def HasSW64Mul : Predicate<"Subtarget.calVersion()"
"< CAL_VERSION_SC_139">;
// Predicate that is set to true if 64bit Div/Mod is supported in the IL or not
def HasHW64DivMod : Predicate<"Subtarget.device()"
"->usesHardware(AMDILDeviceInfo::HW64BitDivMod)">;
"->usesHardware(AMDGPUDeviceInfo::HW64BitDivMod)">;
def HasSW64DivMod : Predicate<"Subtarget.device()"
"->usesSoftware(AMDILDeviceInfo::HW64BitDivMod)">;
"->usesSoftware(AMDGPUDeviceInfo::HW64BitDivMod)">;
// Predicate that is set to true if 64bit pointer are used.
def Has64BitPtr : Predicate<"Subtarget.is64bit()">;

14
src/gallium/drivers/radeon/AMDILIntrinsicInfo.cpp
View file

@ -24,13 +24,13 @@ using namespace llvm;
#include "AMDGPUGenIntrinsics.inc"
#undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
AMDILIntrinsicInfo::AMDILIntrinsicInfo(TargetMachine *tm)
AMDGPUIntrinsicInfo::AMDGPUIntrinsicInfo(TargetMachine *tm)
: TargetIntrinsicInfo(), mTM(tm)
{
}
std::string
AMDILIntrinsicInfo::getName(unsigned int IntrID, Type **Tys,
AMDGPUIntrinsicInfo::getName(unsigned int IntrID, Type **Tys,
unsigned int numTys) const
{
static const char* const names[] = {
@ -40,11 +40,11 @@ AMDILIntrinsicInfo::getName(unsigned int IntrID, Type **Tys,
};
//assert(!isOverloaded(IntrID)
//&& "AMDIL Intrinsics are not overloaded");
//&& "AMDGPU Intrinsics are not overloaded");
if (IntrID < Intrinsic::num_intrinsics) {
return 0;
}
assert(IntrID < AMDGPUIntrinsic::num_AMDIL_intrinsics
assert(IntrID < AMDGPUIntrinsic::num_AMDGPU_intrinsics
&& "Invalid intrinsic ID");
std::string Result(names[IntrID - Intrinsic::num_intrinsics]);
@ -52,7 +52,7 @@ AMDILIntrinsicInfo::getName(unsigned int IntrID, Type **Tys,
}
unsigned int
AMDILIntrinsicInfo::lookupName(const char *Name, unsigned int Len) const
AMDGPUIntrinsicInfo::lookupName(const char *Name, unsigned int Len) const
{
#define GET_FUNCTION_RECOGNIZER
#include "AMDGPUGenIntrinsics.inc"
@ -68,7 +68,7 @@ AMDILIntrinsicInfo::lookupName(const char *Name, unsigned int Len) const
}
bool
AMDILIntrinsicInfo::isOverloaded(unsigned id) const
AMDGPUIntrinsicInfo::isOverloaded(unsigned id) const
{
// Overload Table
#define GET_INTRINSIC_OVERLOAD_TABLE
@ -82,7 +82,7 @@ AMDILIntrinsicInfo::isOverloaded(unsigned id) const
#undef GET_INTRINSIC_ATTRIBUTES
Function*
AMDILIntrinsicInfo::getDeclaration(Module *M, unsigned IntrID,
AMDGPUIntrinsicInfo::getDeclaration(Module *M, unsigned IntrID,
Type **Tys,
unsigned numTys) const
{

10
src/gallium/drivers/radeon/AMDILIntrinsicInfo.h
View file

@ -20,20 +20,20 @@ namespace llvm {
class TargetMachine;
namespace AMDGPUIntrinsic {
enum ID {
last_non_AMDIL_intrinsic = Intrinsic::num_intrinsics - 1,
last_non_AMDGPU_intrinsic = Intrinsic::num_intrinsics - 1,
#define GET_INTRINSIC_ENUM_VALUES
#include "AMDGPUGenIntrinsics.inc"
#undef GET_INTRINSIC_ENUM_VALUES
, num_AMDIL_intrinsics
, num_AMDGPU_intrinsics
};
}
class AMDILIntrinsicInfo : public TargetIntrinsicInfo {
class AMDGPUIntrinsicInfo : public TargetIntrinsicInfo {
TargetMachine *mTM;
public:
AMDILIntrinsicInfo(TargetMachine *tm);
AMDGPUIntrinsicInfo(TargetMachine *tm);
std::string getName(unsigned int IntrId, Type **Tys = 0,
unsigned int numTys = 0) const;
unsigned int lookupName(const char *Name, unsigned int Len) const;
@ -41,7 +41,7 @@ namespace llvm {
Function *getDeclaration(Module *M, unsigned int ID,
Type **Tys = 0,
unsigned int numTys = 0) const;
}; // AMDILIntrinsicInfo
}; // AMDGPUIntrinsicInfo
}
#endif // _AMDIL_INTRINSICS_H_

34
src/gallium/drivers/radeon/AMDILNIDevice.cpp
View file

@ -12,8 +12,8 @@
using namespace llvm;
AMDILNIDevice::AMDILNIDevice(AMDGPUSubtarget *ST)
: AMDILEvergreenDevice(ST)
AMDGPUNIDevice::AMDGPUNIDevice(AMDGPUSubtarget *ST)
: AMDGPUEvergreenDevice(ST)
{
std::string name = ST->getDeviceName();
if (name == "caicos") {
@ -26,14 +26,14 @@ AMDILNIDevice::AMDILNIDevice(AMDGPUSubtarget *ST)
mDeviceFlag = OCL_DEVICE_BARTS;
}
}
AMDILNIDevice::~AMDILNIDevice()
AMDGPUNIDevice::~AMDGPUNIDevice()
{
}
size_t
AMDILNIDevice::getMaxLDSSize() const
AMDGPUNIDevice::getMaxLDSSize() const
{
if (usesHardware(AMDILDeviceInfo::LocalMem)) {
if (usesHardware(AMDGPUDeviceInfo::LocalMem)) {
return MAX_LDS_SIZE_900;
} else {
return 0;
@ -41,31 +41,31 @@ AMDILNIDevice::getMaxLDSSize() const
}
uint32_t
AMDILNIDevice::getGeneration() const
AMDGPUNIDevice::getGeneration() const
{
return AMDILDeviceInfo::HD6XXX;
return AMDGPUDeviceInfo::HD6XXX;
}
AMDILCaymanDevice::AMDILCaymanDevice(AMDGPUSubtarget *ST)
: AMDILNIDevice(ST)
AMDGPUCaymanDevice::AMDGPUCaymanDevice(AMDGPUSubtarget *ST)
: AMDGPUNIDevice(ST)
{
setCaps();
}
AMDILCaymanDevice::~AMDILCaymanDevice()
AMDGPUCaymanDevice::~AMDGPUCaymanDevice()
{
}
void
AMDILCaymanDevice::setCaps()
AMDGPUCaymanDevice::setCaps()
{
if (mSTM->isOverride(AMDILDeviceInfo::DoubleOps)) {
mHWBits.set(AMDILDeviceInfo::DoubleOps);
mHWBits.set(AMDILDeviceInfo::FMA);
if (mSTM->isOverride(AMDGPUDeviceInfo::DoubleOps)) {
mHWBits.set(AMDGPUDeviceInfo::DoubleOps);
mHWBits.set(AMDGPUDeviceInfo::FMA);
}
mHWBits.set(AMDILDeviceInfo::Signed24BitOps);
mSWBits.reset(AMDILDeviceInfo::Signed24BitOps);
mSWBits.set(AMDILDeviceInfo::ArenaSegment);
mHWBits.set(AMDGPUDeviceInfo::Signed24BitOps);
mSWBits.reset(AMDGPUDeviceInfo::Signed24BitOps);
mSWBits.set(AMDGPUDeviceInfo::ArenaSegment);
}

28
src/gallium/drivers/radeon/AMDILNIDevice.h
View file

@ -25,35 +25,35 @@ namespace llvm {
// NI generation of devices and their respective sub classes
//===---------------------------------------------------------------------===//
// The AMDILNIDevice is the base class for all Northern Island series of
// cards. It is very similiar to the AMDILEvergreenDevice, with the major
// The AMDGPUNIDevice is the base class for all Northern Island series of
// cards. It is very similiar to the AMDGPUEvergreenDevice, with the major
// exception being differences in wavefront size and hardware capabilities. The
// NI devices are all 64 wide wavefronts and also add support for signed 24 bit
// integer operations
class AMDILNIDevice : public AMDILEvergreenDevice {
class AMDGPUNIDevice : public AMDGPUEvergreenDevice {
public:
AMDILNIDevice(AMDGPUSubtarget*);
virtual ~AMDILNIDevice();
AMDGPUNIDevice(AMDGPUSubtarget*);
virtual ~AMDGPUNIDevice();
virtual size_t getMaxLDSSize() const;
virtual uint32_t getGeneration() const;
protected:
}; // AMDILNIDevice
}; // AMDGPUNIDevice
// Just as the AMDILCypressDevice is the double capable version of the
// AMDILEvergreenDevice, the AMDILCaymanDevice is the double capable version of
// the AMDILNIDevice. The other major difference that is not as useful from
// Just as the AMDGPUCypressDevice is the double capable version of the
// AMDGPUEvergreenDevice, the AMDGPUCaymanDevice is the double capable version of
// the AMDGPUNIDevice. The other major difference that is not as useful from
// standpoint is that the Cayman Device has 4 wide ALU's, whereas the rest of the
// NI family is a 5 wide.
class AMDILCaymanDevice: public AMDILNIDevice {
class AMDGPUCaymanDevice: public AMDGPUNIDevice {
public:
AMDILCaymanDevice(AMDGPUSubtarget*);
virtual ~AMDILCaymanDevice();
AMDGPUCaymanDevice(AMDGPUSubtarget*);
virtual ~AMDGPUCaymanDevice();
private:
virtual void setCaps();
}; // AMDILCaymanDevice
}; // AMDGPUCaymanDevice
static const unsigned int MAX_LDS_SIZE_900 = AMDILDevice::MAX_LDS_SIZE_800;
static const unsigned int MAX_LDS_SIZE_900 = AMDGPUDevice::MAX_LDS_SIZE_800;
} // namespace llvm
#endif // _AMDILNIDEVICE_H_

98
src/gallium/drivers/radeon/AMDILPeepholeOptimizer.cpp
View file

@ -37,12 +37,12 @@ namespace {
class OpaqueType;
class LLVM_LIBRARY_VISIBILITY AMDILPeepholeOpt : public FunctionPass {
class LLVM_LIBRARY_VISIBILITY AMDGPUPeepholeOpt : public FunctionPass {
public:
TargetMachine &TM;
static char ID;
AMDILPeepholeOpt(TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
~AMDILPeepholeOpt();
AMDGPUPeepholeOpt(TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
~AMDGPUPeepholeOpt();
const char *getPassName() const;
bool runOnFunction(Function &F);
bool doInitialization(Module &M);
@ -128,8 +128,8 @@ private:
const AMDGPUSubtarget *mSTM;
SmallVector< std::pair<CallInst *, Function *>, 16> atomicFuncs;
SmallVector<CallInst *, 16> isConstVec;
}; // class AMDILPeepholeOpt
char AMDILPeepholeOpt::ID = 0;
}; // class AMDGPUPeepholeOpt
char AMDGPUPeepholeOpt::ID = 0;
// A template function that has two levels of looping before calling the
// function with a pointer to the current iterator.
@ -153,13 +153,13 @@ Function safeNestedForEach(InputIterator First, InputIterator Last,
namespace llvm {
FunctionPass *
createAMDILPeepholeOpt(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
createAMDGPUPeepholeOpt(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
{
return new AMDILPeepholeOpt(tm AMDIL_OPT_LEVEL_VAR);
return new AMDGPUPeepholeOpt(tm AMDIL_OPT_LEVEL_VAR);
}
} // llvm namespace
AMDILPeepholeOpt::AMDILPeepholeOpt(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
AMDGPUPeepholeOpt::AMDGPUPeepholeOpt(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
: FunctionPass(ID), TM(tm)
{
mDebug = false;
@ -167,14 +167,14 @@ AMDILPeepholeOpt::AMDILPeepholeOpt(TargetMachine &tm AMDIL_OPT_LEVEL_DECL)
}
AMDILPeepholeOpt::~AMDILPeepholeOpt()
AMDGPUPeepholeOpt::~AMDGPUPeepholeOpt()
{
}
const char *
AMDILPeepholeOpt::getPassName() const
AMDGPUPeepholeOpt::getPassName() const
{
return "AMDIL PeepHole Optimization Pass";
return "AMDGPU PeepHole Optimization Pass";
}
bool
@ -207,7 +207,7 @@ containsPointerType(Type *Ty)
}
bool
AMDILPeepholeOpt::dumpAllIntoArena(Function &F)
AMDGPUPeepholeOpt::dumpAllIntoArena(Function &F)
{
bool dumpAll = false;
for (Function::const_arg_iterator cab = F.arg_begin(),
@ -233,7 +233,7 @@ AMDILPeepholeOpt::dumpAllIntoArena(Function &F)
return dumpAll;
}
void
AMDILPeepholeOpt::doIsConstCallConversionIfNeeded()
AMDGPUPeepholeOpt::doIsConstCallConversionIfNeeded()
{
if (isConstVec.empty()) {
return;
@ -250,7 +250,7 @@ AMDILPeepholeOpt::doIsConstCallConversionIfNeeded()
isConstVec.clear();
}
void
AMDILPeepholeOpt::doAtomicConversionIfNeeded(Function &F)
AMDGPUPeepholeOpt::doAtomicConversionIfNeeded(Function &F)
{
// Don't do anything if we don't have any atomic operations.
if (atomicFuncs.empty()) {
@ -271,7 +271,7 @@ AMDILPeepholeOpt::doAtomicConversionIfNeeded(Function &F)
}
bool
AMDILPeepholeOpt::runOnFunction(Function &MF)
AMDGPUPeepholeOpt::runOnFunction(Function &MF)
{
mChanged = false;
mF = &MF;
@ -282,7 +282,7 @@ AMDILPeepholeOpt::runOnFunction(Function &MF)
mCTX = &MF.getType()->getContext();
mConvertAtomics = true;
safeNestedForEach(MF.begin(), MF.end(), MF.begin()->begin(),
std::bind1st(std::mem_fun(&AMDILPeepholeOpt::instLevelOptimizations),
std::bind1st(std::mem_fun(&AMDGPUPeepholeOpt::instLevelOptimizations),
this));
doAtomicConversionIfNeeded(MF);
@ -295,7 +295,7 @@ AMDILPeepholeOpt::runOnFunction(Function &MF)
}
bool
AMDILPeepholeOpt::optimizeCallInst(BasicBlock::iterator *bbb)
AMDGPUPeepholeOpt::optimizeCallInst(BasicBlock::iterator *bbb)
{
Instruction *inst = (*bbb);
CallInst *CI = dyn_cast<CallInst>(inst);
@ -372,8 +372,8 @@ AMDILPeepholeOpt::optimizeCallInst(BasicBlock::iterator *bbb)
atomicFuncs.push_back(std::make_pair <CallInst*, Function*>(CI, F));
}
if (!mSTM->device()->isSupported(AMDILDeviceInfo::ArenaSegment)
&& !mSTM->device()->isSupported(AMDILDeviceInfo::MultiUAV)) {
if (!mSTM->device()->isSupported(AMDGPUDeviceInfo::ArenaSegment)
&& !mSTM->device()->isSupported(AMDGPUDeviceInfo::MultiUAV)) {
return false;
}
if (!mConvertAtomics) {
@ -387,7 +387,7 @@ AMDILPeepholeOpt::optimizeCallInst(BasicBlock::iterator *bbb)
}
bool
AMDILPeepholeOpt::setupBitInsert(Instruction *base,
AMDGPUPeepholeOpt::setupBitInsert(Instruction *base,
Instruction *&src,
Constant *&mask,
Constant *&shift)
@ -440,7 +440,7 @@ AMDILPeepholeOpt::setupBitInsert(Instruction *base,
return true;
}
bool
AMDILPeepholeOpt::optimizeBitInsert(Instruction *inst)
AMDGPUPeepholeOpt::optimizeBitInsert(Instruction *inst)
{
if (!inst) {
return false;
@ -463,7 +463,7 @@ AMDILPeepholeOpt::optimizeBitInsert(Instruction *inst)
// (A & B) | ((D & E) << F) when B ^ E == 0 && (1 << F) >= B
// (A & B) | (D << F) when (1 << F) >= B
// (A << C) | (D & E) when (1 << C) >= E
if (mSTM->device()->getGeneration() == AMDILDeviceInfo::HD4XXX) {
if (mSTM->device()->getGeneration() == AMDGPUDeviceInfo::HD4XXX) {
// The HD4XXX hardware doesn't support the ubit_insert instruction.
return false;
}
@ -680,7 +680,7 @@ AMDILPeepholeOpt::optimizeBitInsert(Instruction *inst)
}
bool
AMDILPeepholeOpt::optimizeBitExtract(Instruction *inst)
AMDGPUPeepholeOpt::optimizeBitExtract(Instruction *inst)
{
if (!inst) {
return false;
@ -703,7 +703,7 @@ AMDILPeepholeOpt::optimizeBitExtract(Instruction *inst)
// __amdil_ubit_extract(log2(C), B, A) The function __amdil_[u|i]bit_extract
// can be found in Section 7.9 of the ATI IL spec of the stream SDK for
// Evergreen hardware.
if (mSTM->device()->getGeneration() == AMDILDeviceInfo::HD4XXX) {
if (mSTM->device()->getGeneration() == AMDGPUDeviceInfo::HD4XXX) {
// This does not work on HD4XXX hardware.
return false;
}
@ -839,7 +839,7 @@ AMDILPeepholeOpt::optimizeBitExtract(Instruction *inst)
}
bool
AMDILPeepholeOpt::expandBFI(CallInst *CI)
AMDGPUPeepholeOpt::expandBFI(CallInst *CI)
{
if (!CI) {
return false;
@ -878,7 +878,7 @@ AMDILPeepholeOpt::expandBFI(CallInst *CI)
}
bool
AMDILPeepholeOpt::expandBFM(CallInst *CI)
AMDGPUPeepholeOpt::expandBFM(CallInst *CI)
{
if (!CI) {
return false;
@ -922,7 +922,7 @@ AMDILPeepholeOpt::expandBFM(CallInst *CI)
}
bool
AMDILPeepholeOpt::instLevelOptimizations(BasicBlock::iterator *bbb)
AMDGPUPeepholeOpt::instLevelOptimizations(BasicBlock::iterator *bbb)
{
Instruction *inst = (*bbb);
if (optimizeCallInst(bbb)) {
@ -940,7 +940,7 @@ AMDILPeepholeOpt::instLevelOptimizations(BasicBlock::iterator *bbb)
return false;
}
bool
AMDILPeepholeOpt::correctMisalignedMemOp(Instruction *inst)
AMDGPUPeepholeOpt::correctMisalignedMemOp(Instruction *inst)
{
LoadInst *linst = dyn_cast<LoadInst>(inst);
StoreInst *sinst = dyn_cast<StoreInst>(inst);
@ -974,7 +974,7 @@ AMDILPeepholeOpt::correctMisalignedMemOp(Instruction *inst)
return false;
}
bool
AMDILPeepholeOpt::isSigned24BitOps(CallInst *CI)
AMDGPUPeepholeOpt::isSigned24BitOps(CallInst *CI)
{
if (!CI) {
return false;
@ -985,14 +985,14 @@ AMDILPeepholeOpt::isSigned24BitOps(CallInst *CI)
&& namePrefix != "__amdil__imul24_high") {
return false;
}
if (mSTM->device()->usesHardware(AMDILDeviceInfo::Signed24BitOps)) {
if (mSTM->device()->usesHardware(AMDGPUDeviceInfo::Signed24BitOps)) {
return false;
}
return true;
}
void
AMDILPeepholeOpt::expandSigned24BitOps(CallInst *CI)
AMDGPUPeepholeOpt::expandSigned24BitOps(CallInst *CI)
{
assert(isSigned24BitOps(CI) && "Must be a "
"signed 24 bit operation to call this function!");
@ -1064,7 +1064,7 @@ AMDILPeepholeOpt::expandSigned24BitOps(CallInst *CI)
}
bool
AMDILPeepholeOpt::isRWGLocalOpt(CallInst *CI)
AMDGPUPeepholeOpt::isRWGLocalOpt(CallInst *CI)
{
return (CI != NULL
&& CI->getOperand(CI->getNumOperands() - 1)->getName()
@ -1072,12 +1072,12 @@ AMDILPeepholeOpt::isRWGLocalOpt(CallInst *CI)
}
bool
AMDILPeepholeOpt::convertAccurateDivide(CallInst *CI)
AMDGPUPeepholeOpt::convertAccurateDivide(CallInst *CI)
{
if (!CI) {
return false;
}
if (mSTM->device()->getGeneration() == AMDILDeviceInfo::HD6XXX
if (mSTM->device()->getGeneration() == AMDGPUDeviceInfo::HD6XXX
&& (mSTM->getDeviceName() == "cayman")) {
return false;
}
@ -1086,7 +1086,7 @@ AMDILPeepholeOpt::convertAccurateDivide(CallInst *CI)
}
void
AMDILPeepholeOpt::expandAccurateDivide(CallInst *CI)
AMDGPUPeepholeOpt::expandAccurateDivide(CallInst *CI)
{
assert(convertAccurateDivide(CI)
&& "expanding accurate divide can only happen if it is expandable!");
@ -1097,7 +1097,7 @@ AMDILPeepholeOpt::expandAccurateDivide(CallInst *CI)
}
bool
AMDILPeepholeOpt::propagateSamplerInst(CallInst *CI)
AMDGPUPeepholeOpt::propagateSamplerInst(CallInst *CI)
{
if (optLevel != CodeGenOpt::None) {
return false;
@ -1125,7 +1125,7 @@ AMDILPeepholeOpt::propagateSamplerInst(CallInst *CI)
return false;
}
if (lInst->getPointerAddressSpace() != AMDILAS::PRIVATE_ADDRESS) {
if (lInst->getPointerAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
return false;
}
@ -1152,26 +1152,26 @@ AMDILPeepholeOpt::propagateSamplerInst(CallInst *CI)
}
bool
AMDILPeepholeOpt::doInitialization(Module &M)
AMDGPUPeepholeOpt::doInitialization(Module &M)
{
return false;
}
bool
AMDILPeepholeOpt::doFinalization(Module &M)
AMDGPUPeepholeOpt::doFinalization(Module &M)
{
return false;
}
void
AMDILPeepholeOpt::getAnalysisUsage(AnalysisUsage &AU) const
AMDGPUPeepholeOpt::getAnalysisUsage(AnalysisUsage &AU) const
{
AU.addRequired<MachineFunctionAnalysis>();
FunctionPass::getAnalysisUsage(AU);
AU.setPreservesAll();
}
size_t AMDILPeepholeOpt::getTypeSize(Type * const T, bool dereferencePtr) {
size_t AMDGPUPeepholeOpt::getTypeSize(Type * const T, bool dereferencePtr) {
size_t size = 0;
if (!T) {
return size;
@ -1209,7 +1209,7 @@ size_t AMDILPeepholeOpt::getTypeSize(Type * const T, bool dereferencePtr) {
return size;
}
size_t AMDILPeepholeOpt::getTypeSize(StructType * const ST,
size_t AMDGPUPeepholeOpt::getTypeSize(StructType * const ST,
bool dereferencePtr) {
size_t size = 0;
if (!ST) {
@ -1225,37 +1225,37 @@ size_t AMDILPeepholeOpt::getTypeSize(StructType * const ST,
return size;
}
size_t AMDILPeepholeOpt::getTypeSize(IntegerType * const IT,
size_t AMDGPUPeepholeOpt::getTypeSize(IntegerType * const IT,
bool dereferencePtr) {
return IT ? (IT->getBitWidth() >> 3) : 0;
}
size_t AMDILPeepholeOpt::getTypeSize(FunctionType * const FT,
size_t AMDGPUPeepholeOpt::getTypeSize(FunctionType * const FT,
bool dereferencePtr) {
assert(0 && "Should not be able to calculate the size of an function type");
return 0;
}
size_t AMDILPeepholeOpt::getTypeSize(ArrayType * const AT,
size_t AMDGPUPeepholeOpt::getTypeSize(ArrayType * const AT,
bool dereferencePtr) {
return (size_t)(AT ? (getTypeSize(AT->getElementType(),
dereferencePtr) * AT->getNumElements())
: 0);
}
size_t AMDILPeepholeOpt::getTypeSize(VectorType * const VT,
size_t AMDGPUPeepholeOpt::getTypeSize(VectorType * const VT,
bool dereferencePtr) {
return VT ? (VT->getBitWidth() >> 3) : 0;
}
size_t AMDILPeepholeOpt::getTypeSize(PointerType * const PT,
size_t AMDGPUPeepholeOpt::getTypeSize(PointerType * const PT,
bool dereferencePtr) {
if (!PT) {
return 0;
}
Type *CT = PT->getElementType();
if (CT->getTypeID() == Type::StructTyID &&
PT->getAddressSpace() == AMDILAS::PRIVATE_ADDRESS) {
PT->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
return getTypeSize(dyn_cast<StructType>(CT));
} else if (dereferencePtr) {
size_t size = 0;
@ -1268,7 +1268,7 @@ size_t AMDILPeepholeOpt::getTypeSize(PointerType * const PT,
}
}
size_t AMDILPeepholeOpt::getTypeSize(OpaqueType * const OT,
size_t AMDGPUPeepholeOpt::getTypeSize(OpaqueType * const OT,
bool dereferencePtr) {
//assert(0 && "Should not be able to calculate the size of an opaque type");
return 4;

16
src/gallium/drivers/radeon/AMDILSIDevice.cpp
View file

@ -13,18 +13,18 @@
using namespace llvm;
AMDILSIDevice::AMDILSIDevice(AMDGPUSubtarget *ST)
: AMDILEvergreenDevice(ST)
AMDGPUSIDevice::AMDGPUSIDevice(AMDGPUSubtarget *ST)
: AMDGPUEvergreenDevice(ST)
{
}
AMDILSIDevice::~AMDILSIDevice()
AMDGPUSIDevice::~AMDGPUSIDevice()
{
}
size_t
AMDILSIDevice::getMaxLDSSize() const
AMDGPUSIDevice::getMaxLDSSize() const
{
if (usesHardware(AMDILDeviceInfo::LocalMem)) {
if (usesHardware(AMDGPUDeviceInfo::LocalMem)) {
return MAX_LDS_SIZE_900;
} else {
return 0;
@ -32,13 +32,13 @@ AMDILSIDevice::getMaxLDSSize() const
}
uint32_t
AMDILSIDevice::getGeneration() const
AMDGPUSIDevice::getGeneration() const
{
return AMDILDeviceInfo::HD7XXX;
return AMDGPUDeviceInfo::HD7XXX;
}
std::string
AMDILSIDevice::getDataLayout() const
AMDGPUSIDevice::getDataLayout() const
{
return std::string("e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16"
"-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"

12
src/gallium/drivers/radeon/AMDILSIDevice.h
View file

@ -25,21 +25,21 @@ namespace llvm {
// SI generation of devices and their respective sub classes
//===---------------------------------------------------------------------===//
// The AMDILSIDevice is the base class for all Northern Island series of
// cards. It is very similiar to the AMDILEvergreenDevice, with the major
// The AMDGPUSIDevice is the base class for all Northern Island series of
// cards. It is very similiar to the AMDGPUEvergreenDevice, with the major
// exception being differences in wavefront size and hardware capabilities. The
// SI devices are all 64 wide wavefronts and also add support for signed 24 bit
// integer operations
class AMDILSIDevice : public AMDILEvergreenDevice {
class AMDGPUSIDevice : public AMDGPUEvergreenDevice {
public:
AMDILSIDevice(AMDGPUSubtarget*);
virtual ~AMDILSIDevice();
AMDGPUSIDevice(AMDGPUSubtarget*);
virtual ~AMDGPUSIDevice();
virtual size_t getMaxLDSSize() const;
virtual uint32_t getGeneration() const;
virtual std::string getDataLayout() const;
protected:
}; // AMDILSIDevice
}; // AMDGPUSIDevice
} // namespace llvm
#endif // _AMDILSIDEVICE_H_

14
src/gallium/drivers/radeon/R600Instructions.td
View file

@ -193,7 +193,7 @@ def load_param : PatFrag<(ops node:$ptr),
const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
if (Src) {
PointerType * PT = dyn_cast<PointerType>(Src->getType());
return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS;
return PT && PT->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS;
}
return false;
}]>;
@ -229,23 +229,23 @@ def load_param : PatFrag<(ops node:$ptr),
//}
*/
def isR600 : Predicate<"Subtarget.device()"
"->getGeneration() == AMDILDeviceInfo::HD4XXX">;
"->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
def isR700 : Predicate<"Subtarget.device()"
"->getGeneration() == AMDILDeviceInfo::HD4XXX &&"
"->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
"Subtarget.device()->getDeviceFlag()"
">= OCL_DEVICE_RV710">;
def isEG : Predicate<"Subtarget.device()"
"->getGeneration() >= AMDILDeviceInfo::HD5XXX && "
"->getGeneration() >= AMDGPUDeviceInfo::HD5XXX && "
"Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">;
def isCayman : Predicate<"Subtarget.device()"
"->getDeviceFlag() == OCL_DEVICE_CAYMAN">;
def isEGorCayman : Predicate<"Subtarget.device()"
"->getGeneration() == AMDILDeviceInfo::HD5XXX"
"->getGeneration() == AMDGPUDeviceInfo::HD5XXX"
"|| Subtarget.device()->getGeneration() =="
"AMDILDeviceInfo::HD6XXX">;
"AMDGPUDeviceInfo::HD6XXX">;
def isR600toCayman : Predicate<
"Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">;
"Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX">;
let Predicates = [isR600toCayman] in {

8
src/gallium/drivers/radeon/R600KernelParameters.cpp
View file

@ -249,9 +249,9 @@ void R600KernelParameters::Propagate(Value* V, const Twine& Name, bool IsIndirec
unsigned Addrspace;
if (IsIndirect) {
Addrspace = AMDILAS::PARAM_I_ADDRESS;
Addrspace = AMDGPUAS::PARAM_I_ADDRESS;
} else {
Addrspace = AMDILAS::PARAM_D_ADDRESS;
Addrspace = AMDGPUAS::PARAM_D_ADDRESS;
}
if (GEP and GEP->getType()->getAddressSpace() != Addrspace) {
@ -321,9 +321,9 @@ Value* R600KernelParameters::ConstantRead(Function *Fun, Param &P) {
unsigned Addrspace;
if (P.IsIndirect) {
Addrspace = AMDILAS::PARAM_I_ADDRESS;
Addrspace = AMDGPUAS::PARAM_I_ADDRESS;
} else {
Addrspace = AMDILAS::PARAM_D_ADDRESS;
Addrspace = AMDGPUAS::PARAM_D_ADDRESS;
}
Argument *Arg = dyn_cast<Argument>(P.Val);

4
src/gallium/drivers/radeon/SIInstructions.td
View file

@ -13,7 +13,7 @@ def load_user_sgpr : PatFrag<(ops node:$ptr),
const Value *Src = cast<LoadSDNode>(N)->getSrcValue();
if (Src) {
PointerType * PT = dyn_cast<PointerType>(Src->getType());
return PT && PT->getAddressSpace() == AMDILAS::USER_SGPR_ADDRESS;
return PT && PT->getAddressSpace() == AMDGPUAS::USER_SGPR_ADDRESS;
}
return false;
}]
@ -21,7 +21,7 @@ def load_user_sgpr : PatFrag<(ops node:$ptr),
def isSI : Predicate<"Subtarget.device()"
"->getGeneration() == AMDILDeviceInfo::HD7XXX">;
"->getGeneration() == AMDGPUDeviceInfo::HD7XXX">;
let Predicates = [isSI] in {