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Author SHA1 Message Date
Dave Airlie
e7d06a55c5 radeon: move debug symbol add DRI2 2009-01-14 15:21:45 +10:00
Dave Airlie
61da612a4f r300: start moving new r300 cmdbuf into common code 2009-01-14 15:14:09 +10:00
Dave Airlie
23295cf8e8 radeon/r200/r300: consolidate swap buffers 2009-01-14 13:38:12 +10:00
Dave Airlie
44b916b2c0 radeon: remove old lock code 2009-01-14 13:38:03 +10:00
Dave Airlie
7e5e327cea radeon/r200/r300: consolidate the buffer copy/flip code into one place 2009-01-14 13:23:24 +10:00
Dave Airlie
d29e96bf33 radeon/r200/r300: attempt to move lock to common code 2009-01-14 12:04:00 +10:00
Dave Airlie
4637235183 radeon/r200/r300: initial attempt to convert to common context code 2009-01-14 10:54:52 +10:00
Dave Airlie
0217ed2cf9 radeon/r200: move more stuff closer together in context 2009-01-14 08:40:15 +10:00
Dave Airlie
b6e4869069 radeon/r200: move state atom to common header 2009-01-14 06:28:43 +10:00
Dave Airlie
692ca82116 radeon/r200: start splitting out commonalities into separate headers 2009-01-13 22:55:27 +10:00
Dave Airlie
4b9a09e9f6 radeon: use bo_wait to wait for all buffers to be rendered to 
Not 100% sure this is correct, but its what Intel does and its better than
CP_IDLE.
 2009-01-13 16:50:15 +10:00
Kristian Høgsberg
d67987b0d1 Bump dri2proto requirement to 1.99.3, drop CopyRegion bitmask from protocol. 
(cherry picked from commit 154a9e5317)
 2009-01-11 09:45:04 +10:00
Dave Airlie
efe68930dc radeon/r300: add code to setup r300 vs r500 using pci device from kernel 2009-01-11 09:47:38 +10:00
Dave Airlie
2a287ddd32 r300: disable settexoffset extension on r300 2008-12-22 17:04:39 +10:00
Dave Airlie
d9b325f77e radeon: fix library name for consistency 2008-12-22 12:28:16 +10:00
Dave Airlie
e14ffb1fa1 radeon: remove start/end offset + cleanup some whitespace 2008-12-22 12:11:21 +10:00
Dave Airlie
a42000bd6b radeon: fixup r500 FP emission for new CS 2008-12-22 11:41:23 +10:00
Dave Airlie
9f2732d312 radeno: hopefully make r200/radeon build 2008-12-21 09:54:35 +10:00
Dave Airlie
72cd2c8c0c radeon: make DRI1 one work with new CS mechanism 2008-12-01 16:39:58 +10:00
Jerome Glisse
9770bb32f5 radeon: cs add print cs callback 2008-11-16 17:59:46 +01:00
Jerome Glisse
f1d98e5127 radeon: fix pointer dangling 2008-11-16 17:58:43 +01:00
Jerome Glisse
56c458e0f2 radeon: update to libdrm-radeon API changes 2008-11-15 10:40:32 +01:00
Jerome Glisse
5b79c18c83 radeon: dri2 don't forget to free buffer 2008-11-14 11:26:17 +01:00
Jerome Glisse
93a9d2f18d r300: release bo from pixmap 2008-11-14 11:26:17 +01:00
Jerome Glisse
c26ec97b13 r300: convert to new relocations format (see libdrm-radeon) 2008-11-14 11:26:17 +01:00
Jerome Glisse
d07d137931 r300: SetTex extension support 2008-11-14 11:26:17 +01:00
Jerome Glisse
3b43c28195 r300: cs + DRI2 support 
If DRI2 is enabled then switch cmd assembly to directly build
hw packet.
 2008-11-14 11:26:17 +01:00
Jerome Glisse
e5d5dab8c0 r300: bo and cs abstraction. 
This abstract memory management and command stream building so we
can use different backend either legacy one which use old pathway
or a new one like with a new memory manager. This works was done by :

Nicolai Haehnle
Dave Airlie
Jerome Glisse
 2008-11-14 11:26:17 +01:00
Brian Paul
80d6379722 mesa: no longer need Writemask field in GLSL IR nodes 
The Swizzle and Size fields carry all the info we need now.
 2008-11-13 18:19:12 -07:00
Brian Paul
3a7ed9779b mesa: revamp GLSL instruction emit code 
This is a step toward better array handling code.  In particular, when more
than one operand of an instruction uses indirect addressing, we'll need some
temporary instructions and registers.  By converting IR storage to instruction
operands all in one place (emit_instruction()) we can be smarter about this.

Also, somewhat better handling of dst register swizzle/writemask handling.
This results in tighter writemasks on some instructions which is good for
SOA execution.

And, cleaner instruction commenting with inst_comment().

Next: remove some more dead code and additional clean-ups...
 2008-11-13 18:19:12 -07:00
Brian Paul
610c2461ce mesa: make writemask_string() non-static 2008-11-13 18:19:12 -07:00
Brian Paul
4c167f8fc1 mesa: remove some do-nothing GLSL code 2008-11-13 18:19:12 -07:00
Brian Paul
fe984aed5a mesa: fix accidental regression in GLSL built-in texture matrix lookup 
Was broken by commit 9aca9a4b72b2a7b378e50bd88f9c3324d07375ec.
 2008-11-13 18:19:12 -07:00
Brian Paul
d835f415c6 mesa: use the tighter definition of GLSL ftransform() from the gallium branches 2008-11-13 18:19:12 -07:00
Brian Paul
e556cc82f8 mesa: remove unused/obsolete __NormalMatrixTranspose matrix 2008-11-13 18:19:12 -07:00
Brian Paul
47b883e42b mesa: fix bug in GLSL built-in matrix state lookup 2008-11-13 18:19:12 -07:00
Brian Paul
557fde9531 mesa: tweak program register printing for RelAddr case 2008-11-13 18:19:12 -07:00
Alan Hourihane
e4c9aeed8b mesa: fix generation of fixed function state when no vp exists 2008-11-13 13:31:10 +00:00
Eric Anholt
c30eb2c104 i965: Upload state on primitive switch, don't just prepare it. 
This was a regression in 59b2c2adbb that broke
blender, among other apps.
 2008-11-12 13:37:16 -08:00
Eric Anholt
2fc9d671e0 i965: Fix VB refcount leak on aperture overflow. 2008-11-12 13:34:20 -08:00
Eric Anholt
72bbc89534 Add glsync demo program from jbarnes for testing vblank synchronization. 2008-11-12 13:07:23 -08:00
Eric Anholt
62ff7ab720 i965: Fix up VS max_threads for G4X and removing a magic number. 
As far as I can read in the docs, VS threads can be 1:1 with the pairs of
VUE handles allocated for them.  Also, G4X can run twice as many threads as
before (though we won't unless the we bump the preferred URB entries for VS).
 2008-11-12 13:07:23 -08:00
Eric Anholt
9dadfc09a9 i965: Fix up SF max_threads. 
We were dividing the number of URB entries by two to get number of threads,
which looks suspiciously like a copy'n'paste-o from brw_vs_state.c.  Also, the
maximum number of threads is 24, not 12.
 2008-11-12 13:07:23 -08:00
Eric Anholt
82eb7c235d i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads. 
The clip thread could potentially deadlock when processing tristrips since
being moved back to dual-thread mode, as the two threads could each have 4 VUEs
referenced and not be able to allocate another one since SF processing
wasn't able to continue (needing 5 entries before it freed 2).
In constrained URB mode, similar deadlock could even have occurred with
polygons (so we cut back max_threads if we can't handle it any primitive type).
 2008-11-12 13:07:22 -08:00
Eric Anholt
5cb7ba10cc i965: Update WM maximum threads for G4X. 2008-11-12 13:07:22 -08:00
Eric Anholt
d70d62c561 i965: Add a big comment explaining my understanding of URB management. 
It shouldn't offer anything new over what's in the docs (except for G4X notes),
but here it's all in one place.
 2008-11-12 13:07:22 -08:00
Kristian Høgsberg
e1fbb30211 glFlush before CopySubBuffer, fix coordinates and extension name typo. 2008-11-12 15:26:25 -05:00
Hanno Böck
becf3d9272 glx: fix xcb build 2008-11-12 06:56:42 -07:00
Brian Paul
90246d3ea5 mesa: fix version check in dinoshade.c 2008-11-11 14:35:39 -07:00
Brian Paul
f4361540f8 mesa: allow relative indexing into all register files and indirect dst register indexing 2008-11-11 14:35:39 -07:00