New mechanisms to retrieve the GLES and Vulkan driver versions have been
introduced in
- 3029fdde65 (ci/android: Switch to using eglinfo to check GLES implementation, 2025-05-28)
- 3ba9038648 (ci/android: Check Vulkan driver using vulkaninfo, 2025-05-28)
These mechanisms are more robust than the previous one but they do
change the behavior in that the version is not retrieved by an already
running process (e.g. SurfaceFlinger), but by creating new processes
that load the libraries available on the filesystem.
Because of this change of behavior the original version should be
printed **before** pushing the new libraries to the Android guest, so
that developers are able to compare the old and new versions in the logs.
Moreover, the runtime checks do not answer the original question anymore:
"what GLES/VK libraries is surfaceflinger currently using?"
but rather new question:
"what GLES/VK libraries are services going to use when they load?"
So the shell start/stop can very well performed after the version check,
accompanied by a new check on the PID of SurfaceFlinger to be sure that
it has reloaded consequently picking up the new libraries.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35335>
These were a bit of a mixed bag; we had some open-coded cases, and a few
overly permissive code-paths. Anyway, let's stricten this up a bit.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35097>
While ARB_texture_float is indeed supposed to disable clamping, it
should only do so on the APIs where the extension is supported.
Otherwise, we end up disabling clamping also when using GLES 1.x,
which isn't quite what we want.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35097>
These enums are not allowed in GLES1, but would be incorrectly accepted
if running on hardware capable of the functionality even in GLES1. So
let's use the helper that also considers the API, which should fix the
problem.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35097>
These helpers already keep track of what API each extension is available
in. This makes the code easier to read and maintain. Let's use them.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35097>
Before we move a UBO load to a previous location in the block we take a
reference to the instruction after it so we can continue the loop from
there, however, if the load we just moved was already the last instruction
in the block we just want to break the loop right there.
Fixes crashes with shaders from http://flightradar24.com
Fixes: 8998666de7 ("broadcom/compiler: sort constant UBO loads by index and offset")
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35333>
Loosely based on RadeonSI.
This is supposed to be faster because parsing the packet header seems
to be the main bottleneck on GFX12.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35282>
Scalar block layout doesn't allow anything that our memory load/store vectorizer
couldn't create on its own. So I assume whatever reason there was to only
expose this feature on GFX7+ was incorrect or ended up being fixed.
Passes vkcts in CI on tahiti.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35279>
0e3e5146cf ("intel/brw: Use correct instruction for value change check
when coalescing") enabled some new cases that exposed a pre-existing
bug that would turn something like this :
mul.sat(16) %789:F, %787:F, %788:F
mov.g.f0.0(16) %790:F, %789:F
(+f0.0) sel(16) %800:UD, %790:UD, 0u
into this :
mul.sat(16) %790:F, %787:F, %788:F
mov.g.f0.0(16) null:F, null<8,8,1>:F
(+f0.0) sel(16) %800:UD, %790:UD, 0u
The mov[] array can contain the same instruction because it's repeated
for each REG_SIZE writes and a SIMD16 instruction will write 2
REG_SIZE.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0e3e5146cf ("intel/brw: Use correct instruction for value change check when coalescing")
Cc: mesa-stable
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35276>
There's always only the ARF scalar register source, so don't
bother printing other information that won't be used. Matches
the assembler code.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35297>
