Commit graph

16914 commits

Author SHA1 Message Date
Marek Olšák
bfe489c76b r600g: set QUANT_MODE on Cayman too
This fixes piglit/fbo-blit-stretched.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-22 00:31:59 +02:00
Marek Olšák
11e2a41b84 r600g: use CS helpers to emit streamout state
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-22 00:31:59 +02:00
Marek Olšák
669bfaaa1e r600g: remove initialization of unused loop register tables
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-22 00:31:59 +02:00
Marek Olšák
b71701d43e r600g: remove now-unused SURFACE_BASE_UPDATE logic
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-22 00:31:58 +02:00
Marek Olšák
e3ecfecada r600g: remove unused CB registers from register lists
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-22 00:31:58 +02:00
Marek Olšák
c8b06dccff r600g: atomize framebuffer state
Tested on RS880, Evergreen and Cayman.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-22 00:31:58 +02:00
Marek Olšák
b652180107 r600g: don't snoop context state while building shaders
Let's use the shader key describing the state.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-22 00:31:58 +02:00
Tom Stellard
8ed9aaea51 clover: Initialize height and depth to 1 for transfers
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2012-09-21 19:45:17 +00:00
Tom Stellard
024e1732cb pipe-loader: Remove a few debug_printfs
On debug builds these were always being printed.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2012-09-21 19:45:07 +00:00
Tom Stellard
438b1da7e5 radeon/llvm: Handle loads from the constants address space.
Reading from constant memory is not supported yet, so constant reads use
global memory.
2012-09-21 19:30:58 +00:00
Tom Stellard
3882d7b5e4 radeon/llvm: Add support for v4f32 stores on R600 2012-09-21 19:30:58 +00:00
Tom Stellard
e866dbd1b5 radeon/llvm: Add support for i8 reads on R600 2012-09-21 19:30:57 +00:00
Tom Stellard
b282c9611e radeon/llvm: Expand vector fadd and fmul on R600 2012-09-21 19:30:57 +00:00
Tom Stellard
aa8367dd13 radeon/llvm: Add optimization for FP_ROUND 2012-09-21 19:30:57 +00:00
Tom Stellard
87decd6e66 radeon/llvm: Replace AMDGPU pow intrinsic with the llvm version 2012-09-21 19:30:53 +00:00
Brian Paul
58f386b20b gallium: mention PIPE_TIMEOUT_INFINITE in the fence_finish() comment 2012-09-20 09:49:12 -06:00
Brian Paul
0bcad02955 llvmpipe: fix overflow bug in total texture size computation
v2: use uint64_t for the total_size variable, per Jose.

Also add two earlier checks for exceeding the max texture size.
For example a 1K^3 RGBA volume would overflow the lpr->image_stride
variable.

Use simple algebra to avoid overflow in intermediate values.
So instead of "x * y > z" use "x > z / y".

This should work if we happen to be on a platform that doesn't have
64-bit types.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2012-09-20 09:47:09 -06:00
Alex Deucher
7b4aefd3c9 r600g/llvm: rs780/rs880 are r600 asics
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20 11:17:52 -04:00
Tom Stellard
bd8fb9e805 r300/compiler: Use precomputed q values in the register allocator 2012-09-19 19:25:53 -04:00
Tom Stellard
886a4d4a6a r300g: Init regalloc state during context creation
Initializing the regalloc state is expensive, and since it is always
the same for every compile we only need to initialize it once per
context.  This should help improve shader compile times for the driver.
2012-09-19 19:25:53 -04:00
Tom Stellard
9282adcae9 r300/compiler: Don't create register classes for inputs 2012-09-19 19:25:53 -04:00
Tom Stellard
e0f64a837f ra: Add q_values parameter to ra_set_finalize()
This allows the user to pass precomputed q values to the allocator.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-09-19 19:25:53 -04:00
Tom Stellard
69b387fbdc r600g: Invalidate texture cache when creating vertex buffers for compute v2
Compute shaders fetch data from vertex buffers via the texture cache, so
we need to make sure the texture cache is flushed.

v2:
  - Fix rebase mistake
  - Fix spelling in comment

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-09-19 14:58:53 -04:00
Tom Stellard
810345492e r600g: Use LOOP_START_DX10 for loops
LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not limited
to 4096 iterations like the other LOOP_* instructions.  Compute shaders
need to use this instruction, and since we aren't optimizing loops with
the LOOP_CONFIG* registers for pixel and vertex shaders, it seems like
we should just use it for everything.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-09-19 14:58:53 -04:00
Tom Stellard
3e3ca92718 r600g: Set the correct value of COLOR*_DIM for RATs
For buffers (which is what is being used for RATs), the
COLOR*_DIM.WIDTH_MASK field needs to be set to the low 16-bits of the
buffer size, and the COLOR*_DIM.HEIEGHT_MAX needs to be set to the
high bits.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-09-19 14:58:53 -04:00
Tom Stellard
9db64530bb r600g: Make sure to initialize DB_DEPTH_CONTROL register for compute
The kernel CS checker will fail if this register is not initialized.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-09-19 14:58:53 -04:00
Tom Stellard
69d814885b r600g: Add some comments and debug printfs to compute code
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-09-19 14:58:53 -04:00
Tom Stellard
6bd11bc9d5 r600g: Add missing break to case statement 2012-09-19 15:27:32 -04:00
Michal Sciubidlo
0e0c21e00e radeon/llvm: Emit ISA for ALU instructions in the R600 code emitter
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-19 13:17:41 -04:00
Tom Stellard
d525ed1a84 radeon/llvm: Only support 512 constant registers on R600
This is necessary upcoming encoding changes, since we will only be
using 9-bits for register encoding.
2012-09-19 13:11:36 -04:00
Vadim Girlin
9aa8bac98b winsys/radeon: fix relocs caching
Don't cache pointers to elements of reallocatable array.
In some circumstances it caused false cache hits resulting in incorrect
command stream and gpu lockup.

Note: This is a candidate for the stable branches.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-09-19 04:48:16 +04:00
Vincent Lejeune
175fdd7b86 radeon/llvm: Add a fdiv pattern.
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
2012-09-18 18:00:20 +02:00
Vincent Lejeune
12c4526157 radeon/llvm: reserve also corresponding 128bits reg
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
2012-09-18 17:59:51 +02:00
Brian Paul
7d624799b9 softpipe: implement the new can_create_resource() function
And define a SP_MAX_TEXTURE_SIZE value as we do in llvmpipe.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2012-09-17 19:49:27 -06:00
Brian Paul
b9e88c5592 llvmpipe: implement the new can_create_resource() function
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2012-09-17 19:49:27 -06:00
Brian Paul
bd8b43a9f4 gallium: add new pipe_screen::can_create_resource() function
Used to implement proxy textures.  If a gallium driver doesn't implement
this function we'll just continue to use the core Mesa fallback code.

Without this hook we really have no good way to implement OpenGL proxy
textures with gallium drivers.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2012-09-17 19:49:27 -06:00
Brian Paul
df73be9105 llvmpipe: set max cube texture size to 4K x 4K
Before, the limit was 8K.  For 32-bit RGBA that would be require 1.5 GB
of memory (w/out mipmaps).  That's well beyond the LP_MAX_TEXTURE_SIZE
of 1GB.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2012-09-17 19:49:26 -06:00
Tom Stellard
bfd55711c1 radeon/llvm: Inital flow control support for SI
This adds basic flow control support for If-Then-Else blocks using
predicates (stored in the EXEC register) and a predicate stack for
nested flow control.
2012-09-17 21:09:43 +00:00
Xinya Zhang
ef0d7e13d7 r600g: Close a memory leak of llvm byte streams
No regressions found in the tests of opencl-example/run_tests.sh.

Signed-off-by: Xinya Zhang <zxy_thf@hotmail.com>
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-17 21:09:43 +00:00
Tom Stellard
0b1a182905 radeon/llvm: Fix unused variable warning 2012-09-17 21:09:43 +00:00
Tom Stellard
059a56bddb radeon/llvm: Move kernel arg lowering into R600TargetLowering class 2012-09-17 21:09:43 +00:00
Michel Dänzer
14c12ca331 radeon/llvm: Match integer add/sub for SI.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-17 18:05:49 +02:00
Michel Dänzer
8d7dd68d2a radeon/llvm: Complete integer comparison patterns for SI.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-17 18:03:41 +02:00
Michel Dänzer
97d3d25e1c radeon/llvm: Match AMDGPUfract on SI.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-17 18:02:01 +02:00
Michel Dänzer
39fb7faf95 radeon/llvm: Match int_AMDGPU_floor for SI.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-17 17:30:09 +02:00
Michel Dänzer
6d3a1a5361 radeon/llvm: Match vector logical operations on SI.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-17 17:12:08 +02:00
Brian Paul
7b6b447fa3 softpipe: update SP_MAX_TEXTURE_3D_LEVELS comment
9 levels = max size of 256 texels.
2012-09-16 19:00:20 -06:00
José Fonseca
b6c2234c22 Temporarily revert "mesa: remove remaining FEATURE_* defines where protected by API check."
This reverts commit 9f37b405a3.

Fixes windows builds.
2012-09-15 18:18:39 +01:00
Oliver McFadden
9f37b405a3 mesa: remove remaining FEATURE_* defines where protected by API check.
Signed-off-by: Oliver McFadden <oliver.mcfadden@linux.intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-15 12:57:57 +03:00
Christian König
fb541662eb radeon/llvm: Support frint on SI
Gets VDPAUs shaders working again.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-14 17:03:24 +02:00