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r600g: atomize framebuffer state

Browse source 
Tested on RS880, Evergreen and Cayman.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák 2012-09-18 19:42:29 +02:00
parent b652180107
commit c8b06dccff
11 changed files with 676 additions and 880 deletions
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30
src/gallium/drivers/r600/evergreen_compute.c
View file

@ -323,7 +323,6 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout,
int i;
struct r600_resource *onebo = NULL;
struct r600_pipe_state *cb_state;
struct evergreen_compute_resource *resources =
ctx->cs_shader_state.shader->resources;
@ -337,9 +336,32 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout,
ctx->flags |= R600_CONTEXT_CB_FLUSH;
r600_flush_emit(ctx);
/* Emit cb_state */
cb_state = ctx->states[R600_PIPE_STATE_FRAMEBUFFER];
r600_context_pipe_state_emit(ctx, cb_state, RADEON_CP_PACKET3_COMPUTE_MODE);
/* Emit colorbuffers. */
for (i = 0; i < ctx->framebuffer.state.nr_cbufs; i++) {
struct r600_surface *cb = (struct r600_surface*)ctx->framebuffer.state.cbufs[i];
unsigned reloc = r600_context_bo_reloc(ctx, (struct r600_resource*)cb->base.texture,
RADEON_USAGE_READWRITE);
r600_write_compute_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 7);
r600_write_value(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
r600_write_value(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
r600_write_value(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
r600_write_value(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
r600_write_value(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
r600_write_value(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
r600_write_value(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
r600_write_value(cs, reloc);
if (!ctx->keep_tiling_flags) {
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
r600_write_value(cs, reloc);
}
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
r600_write_value(cs, reloc);
}
/* Set CB_TARGET_MASK XXX: Use cb_misc_state */
r600_write_compute_context_reg(cs, R_028238_CB_TARGET_MASK,

31
src/gallium/drivers/r600/evergreen_compute_internal.c
View file

@ -264,10 +264,8 @@ void evergreen_set_rat(
assert((size & 3) == 0);
assert((start & 0xFF) == 0);
struct r600_pipe_state * state = CALLOC_STRUCT(r600_pipe_state);
struct pipe_surface rat_templ;
struct r600_surface *surf;
struct r600_resource *res;
struct r600_context *rctx = pipe->ctx;
COMPUTE_DBG("bind rat: %i \n", id);
@ -281,12 +279,13 @@ void evergreen_set_rat(
rat_templ.u.tex.last_layer = 0;
/* Add the RAT the list of color buffers */
pipe->ctx->framebuffer.cbufs[id] = pipe->ctx->context.create_surface(
pipe->ctx->framebuffer.state.cbufs[id] = pipe->ctx->context.create_surface(
(struct pipe_context *)pipe->ctx,
(struct pipe_resource *)bo, &rat_templ);
/* Update the number of color buffers */
pipe->ctx->nr_cbufs = MAX2(id + 1, pipe->ctx->nr_cbufs);
pipe->ctx->framebuffer.state.nr_cbufs =
MAX2(id + 1, pipe->ctx->framebuffer.state.nr_cbufs);
/* Update the cb_target_mask
* XXX: I think this is a potential spot for bugs once we start doing
@ -294,31 +293,9 @@ void evergreen_set_rat(
* of this driver. */
pipe->ctx->compute_cb_target_mask |= (0xf << (id * 4));
surf = (struct r600_surface*)pipe->ctx->framebuffer.cbufs[id];
res = (struct r600_resource*)surf->base.texture;
surf = (struct r600_surface*)pipe->ctx->framebuffer.state.cbufs[id];
evergreen_init_color_surface(rctx, surf);
/* Get the CB register writes for the RAT */
r600_pipe_state_add_reg_bo(state, R_028C60_CB_COLOR0_BASE + id * 0x3C,
surf->cb_color_base, res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(state, R_028C78_CB_COLOR0_DIM + id * 0x3C,
surf->cb_color_dim);
r600_pipe_state_add_reg_bo(state, R_028C70_CB_COLOR0_INFO + id * 0x3C,
surf->cb_color_info, res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(state, R_028C64_CB_COLOR0_PITCH + id * 0x3C,
surf->cb_color_pitch);
r600_pipe_state_add_reg(state, R_028C68_CB_COLOR0_SLICE + id * 0x3C,
surf->cb_color_slice);
r600_pipe_state_add_reg(state, R_028C6C_CB_COLOR0_VIEW + id * 0x3C,
surf->cb_color_view);
r600_pipe_state_add_reg_bo(state, R_028C74_CB_COLOR0_ATTRIB + id * 0x3C,
surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
/* Add the register blocks to the dirty list */
free(pipe->ctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
pipe->ctx->states[R600_PIPE_STATE_FRAMEBUFFER] = state;
r600_context_pipe_state_set(pipe->ctx, state);
}
void evergreen_set_gds(

304
src/gallium/drivers/r600/evergreen_hw_context.c
View file

@ -33,27 +33,10 @@ static const struct r600_reg cayman_config_reg_list[] = {
};
static const struct r600_reg evergreen_context_reg_list[] = {
{R_028008_DB_DEPTH_VIEW, 0, 0},
{R_028010_DB_RENDER_OVERRIDE2, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028044_DB_STENCIL_INFO, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028058_DB_DEPTH_SIZE, 0, 0},
{R_02805C_DB_DEPTH_SLICE, 0, 0},
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
@ -144,202 +127,54 @@ static const struct r600_reg evergreen_context_reg_list[] = {
{R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
{R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
{R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
{R_028C00_PA_SC_LINE_CNTL, 0, 0},
{R_028C04_PA_SC_AA_CONFIG, 0, 0},
{R_028C08_PA_SU_VTX_CNTL, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, 0, 0},
{R_028C20_PA_SC_AA_SAMPLE_LOCS_1, 0, 0},
{R_028C24_PA_SC_AA_SAMPLE_LOCS_2, 0, 0},
{R_028C28_PA_SC_AA_SAMPLE_LOCS_3, 0, 0},
{R_028C2C_PA_SC_AA_SAMPLE_LOCS_4, 0, 0},
{R_028C30_PA_SC_AA_SAMPLE_LOCS_5, 0, 0},
{R_028C34_PA_SC_AA_SAMPLE_LOCS_6, 0, 0},
{R_028C38_PA_SC_AA_SAMPLE_LOCS_7, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
{R_028C64_CB_COLOR0_PITCH, 0, 0},
{R_028C68_CB_COLOR0_SLICE, 0, 0},
{R_028C6C_CB_COLOR0_VIEW, 0, 0},
{R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
{R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028C78_CB_COLOR0_DIM, 0, 0},
{R_028C7C_CB_COLOR0_CMASK, REG_FLAG_NEED_BO},
{R_028C80_CB_COLOR0_CMASK_SLICE},
{R_028C84_CB_COLOR0_FMASK, REG_FLAG_NEED_BO},
{R_028C88_CB_COLOR0_FMASK_SLICE},
{R_028C8C_CB_COLOR0_CLEAR_WORD0},
{R_028C90_CB_COLOR0_CLEAR_WORD1},
{R_028C94_CB_COLOR0_CLEAR_WORD2},
{R_028C98_CB_COLOR0_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
{R_028CA0_CB_COLOR1_PITCH, 0, 0},
{R_028CA4_CB_COLOR1_SLICE, 0, 0},
{R_028CA8_CB_COLOR1_VIEW, 0, 0},
{R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
{R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028CB4_CB_COLOR1_DIM, 0, 0},
{R_028CB8_CB_COLOR1_CMASK, REG_FLAG_NEED_BO, 0},
{R_028CBC_CB_COLOR1_CMASK_SLICE, 0, 0},
{R_028CC0_CB_COLOR1_FMASK, REG_FLAG_NEED_BO, 0},
{R_028CC4_CB_COLOR1_FMASK_SLICE, 0, 0},
{R_028CC8_CB_COLOR1_CLEAR_WORD0},
{R_028CCC_CB_COLOR1_CLEAR_WORD1},
{R_028CD0_CB_COLOR1_CLEAR_WORD2},
{R_028CD4_CB_COLOR1_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
{R_028CDC_CB_COLOR2_PITCH, 0, 0},
{R_028CE0_CB_COLOR2_SLICE, 0, 0},
{R_028CE4_CB_COLOR2_VIEW, 0, 0},
{R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
{R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028CF0_CB_COLOR2_DIM, 0, 0},
{R_028CF4_CB_COLOR2_CMASK, REG_FLAG_NEED_BO, 0},
{R_028CF8_CB_COLOR2_CMASK_SLICE, 0, 0},
{R_028CFC_CB_COLOR2_FMASK, REG_FLAG_NEED_BO, 0},
{R_028D00_CB_COLOR2_FMASK_SLICE, 0, 0},
{R_028D04_CB_COLOR2_CLEAR_WORD0},
{R_028D08_CB_COLOR2_CLEAR_WORD1},
{R_028D0C_CB_COLOR2_CLEAR_WORD2},
{R_028D10_CB_COLOR2_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
{R_028D18_CB_COLOR3_PITCH, 0, 0},
{R_028D1C_CB_COLOR3_SLICE, 0, 0},
{R_028D20_CB_COLOR3_VIEW, 0, 0},
{R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
{R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028D2C_CB_COLOR3_DIM, 0, 0},
{R_028D30_CB_COLOR3_CMASK, REG_FLAG_NEED_BO},
{R_028D34_CB_COLOR3_CMASK_SLICE},
{R_028D38_CB_COLOR3_FMASK, REG_FLAG_NEED_BO},
{R_028D3C_CB_COLOR3_FMASK_SLICE},
{R_028D40_CB_COLOR3_CLEAR_WORD0},
{R_028D44_CB_COLOR3_CLEAR_WORD1},
{R_028D48_CB_COLOR3_CLEAR_WORD2},
{R_028D4C_CB_COLOR3_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
{R_028D54_CB_COLOR4_PITCH, 0, 0},
{R_028D58_CB_COLOR4_SLICE, 0, 0},
{R_028D5C_CB_COLOR4_VIEW, 0, 0},
{R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
{R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028D68_CB_COLOR4_DIM, 0, 0},
{R_028D6C_CB_COLOR4_CMASK, REG_FLAG_NEED_BO},
{R_028D70_CB_COLOR4_CMASK_SLICE},
{R_028D74_CB_COLOR4_FMASK, REG_FLAG_NEED_BO},
{R_028D78_CB_COLOR4_FMASK_SLICE},
{R_028D7C_CB_COLOR4_CLEAR_WORD0},
{R_028D80_CB_COLOR4_CLEAR_WORD1},
{R_028D84_CB_COLOR4_CLEAR_WORD2},
{R_028D88_CB_COLOR4_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
{R_028D90_CB_COLOR5_PITCH, 0, 0},
{R_028D94_CB_COLOR5_SLICE, 0, 0},
{R_028D98_CB_COLOR5_VIEW, 0, 0},
{R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
{R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028DA4_CB_COLOR5_DIM, 0, 0},
{R_028DA8_CB_COLOR5_CMASK, REG_FLAG_NEED_BO},
{R_028DAC_CB_COLOR5_CMASK_SLICE},
{R_028DB0_CB_COLOR5_FMASK, REG_FLAG_NEED_BO},
{R_028DB4_CB_COLOR5_FMASK_SLICE},
{R_028DB8_CB_COLOR5_CLEAR_WORD0},
{R_028DBC_CB_COLOR5_CLEAR_WORD1},
{R_028DC0_CB_COLOR5_CLEAR_WORD2},
{R_028DC4_CB_COLOR5_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
{R_028DCC_CB_COLOR6_PITCH, 0, 0},
{R_028DD0_CB_COLOR6_SLICE, 0, 0},
{R_028DD4_CB_COLOR6_VIEW, 0, 0},
{R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
{R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028DE0_CB_COLOR6_DIM, 0, 0},
{R_028DE4_CB_COLOR6_CMASK, REG_FLAG_NEED_BO},
{R_028DE8_CB_COLOR6_CMASK_SLICE},
{R_028DEC_CB_COLOR6_FMASK, REG_FLAG_NEED_BO},
{R_028DF0_CB_COLOR6_FMASK_SLICE},
{R_028DF4_CB_COLOR6_CLEAR_WORD0},
{R_028DF8_CB_COLOR6_CLEAR_WORD1},
{R_028DFC_CB_COLOR6_CLEAR_WORD2},
{R_028E00_CB_COLOR6_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
{R_028E08_CB_COLOR7_PITCH, 0, 0},
{R_028E0C_CB_COLOR7_SLICE, 0, 0},
{R_028E10_CB_COLOR7_VIEW, 0, 0},
{R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
{R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028E1C_CB_COLOR7_DIM, 0, 0},
{R_028E20_CB_COLOR7_CMASK, REG_FLAG_NEED_BO},
{R_028E24_CB_COLOR7_CMASK_SLICE},
{R_028E28_CB_COLOR7_FMASK, REG_FLAG_NEED_BO},
{R_028E2C_CB_COLOR7_FMASK_SLICE},
{R_028E30_CB_COLOR7_CLEAR_WORD0},
{R_028E34_CB_COLOR7_CLEAR_WORD1},
{R_028E38_CB_COLOR7_CLEAR_WORD2},
{R_028E3C_CB_COLOR7_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
{R_028E44_CB_COLOR8_PITCH, 0, 0},
{R_028E48_CB_COLOR8_SLICE, 0, 0},
{R_028E4C_CB_COLOR8_VIEW, 0, 0},
{R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0},
{R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028E58_CB_COLOR8_DIM, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0},
{R_028E60_CB_COLOR9_PITCH, 0, 0},
{R_028E64_CB_COLOR9_SLICE, 0, 0},
{R_028E68_CB_COLOR9_VIEW, 0, 0},
{R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0},
{R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028E74_CB_COLOR9_DIM, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0},
{R_028E7C_CB_COLOR10_PITCH, 0, 0},
{R_028E80_CB_COLOR10_SLICE, 0, 0},
{R_028E84_CB_COLOR10_VIEW, 0, 0},
{R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0},
{R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028E90_CB_COLOR10_DIM, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0},
{R_028E98_CB_COLOR11_PITCH, 0, 0},
{R_028E9C_CB_COLOR11_SLICE, 0, 0},
{R_028EA0_CB_COLOR11_VIEW, 0, 0},
{R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0},
{R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028EAC_CB_COLOR11_DIM, 0, 0},
};
static const struct r600_reg cayman_context_reg_list[] = {
{R_028008_DB_DEPTH_VIEW, 0, 0},
{R_028010_DB_RENDER_OVERRIDE2, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028044_DB_STENCIL_INFO, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028058_DB_DEPTH_SIZE, 0, 0},
{R_02805C_DB_DEPTH_SLICE, 0, 0},
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
@ -405,7 +240,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
{R_028798_CB_BLEND6_CONTROL, 0, 0},
{R_02879C_CB_BLEND7_CONTROL, 0, 0},
{R_028800_DB_DEPTH_CONTROL, 0, 0},
{CM_R_028804_DB_EQAA},
{R_028808_CB_COLOR_CONTROL, 0, 0},
{R_02880C_DB_SHADER_CONTROL, 0, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
@ -439,185 +273,47 @@ static const struct r600_reg cayman_context_reg_list[] = {
{R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
{R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
{R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
{CM_R_028BDC_PA_SC_LINE_CNTL, 0, 0},
{CM_R_028BE0_PA_SC_AA_CONFIG, 0, 0},
{CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0},
{CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0, 0},
{CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0, 0},
{CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0, 0},
{CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0, 0},
{CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0, 0},
{CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0, 0},
{CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0, 0},
{CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0, 0},
{CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0, 0},
{CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0, 0},
{CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0, 0},
{CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0, 0},
{CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0, 0},
{CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0, 0},
{CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0, 0},
{CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0},
{R_028C64_CB_COLOR0_PITCH, 0, 0},
{R_028C68_CB_COLOR0_SLICE, 0, 0},
{R_028C6C_CB_COLOR0_VIEW, 0, 0},
{R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
{R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028C78_CB_COLOR0_DIM, 0, 0},
{R_028C7C_CB_COLOR0_CMASK, REG_FLAG_NEED_BO},
{R_028C80_CB_COLOR0_CMASK_SLICE},
{R_028C84_CB_COLOR0_FMASK, REG_FLAG_NEED_BO},
{R_028C88_CB_COLOR0_FMASK_SLICE},
{R_028C8C_CB_COLOR0_CLEAR_WORD0},
{R_028C90_CB_COLOR0_CLEAR_WORD1},
{R_028C94_CB_COLOR0_CLEAR_WORD2},
{R_028C98_CB_COLOR0_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0},
{R_028CA0_CB_COLOR1_PITCH, 0, 0},
{R_028CA4_CB_COLOR1_SLICE, 0, 0},
{R_028CA8_CB_COLOR1_VIEW, 0, 0},
{R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
{R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028CB4_CB_COLOR1_DIM, 0, 0},
{R_028CB8_CB_COLOR1_CMASK, REG_FLAG_NEED_BO, 0},
{R_028CBC_CB_COLOR1_CMASK_SLICE, 0, 0},
{R_028CC0_CB_COLOR1_FMASK, REG_FLAG_NEED_BO, 0},
{R_028CC4_CB_COLOR1_FMASK_SLICE, 0, 0},
{R_028CC8_CB_COLOR1_CLEAR_WORD0},
{R_028CCC_CB_COLOR1_CLEAR_WORD1},
{R_028CD0_CB_COLOR1_CLEAR_WORD2},
{R_028CD4_CB_COLOR1_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0},
{R_028CDC_CB_COLOR2_PITCH, 0, 0},
{R_028CE0_CB_COLOR2_SLICE, 0, 0},
{R_028CE4_CB_COLOR2_VIEW, 0, 0},
{R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
{R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028CF0_CB_COLOR2_DIM, 0, 0},
{R_028CF4_CB_COLOR2_CMASK, REG_FLAG_NEED_BO, 0},
{R_028CF8_CB_COLOR2_CMASK_SLICE, 0, 0},
{R_028CFC_CB_COLOR2_FMASK, REG_FLAG_NEED_BO, 0},
{R_028D00_CB_COLOR2_FMASK_SLICE, 0, 0},
{R_028D04_CB_COLOR2_CLEAR_WORD0},
{R_028D08_CB_COLOR2_CLEAR_WORD1},
{R_028D0C_CB_COLOR2_CLEAR_WORD2},
{R_028D10_CB_COLOR2_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0},
{R_028D18_CB_COLOR3_PITCH, 0, 0},
{R_028D1C_CB_COLOR3_SLICE, 0, 0},
{R_028D20_CB_COLOR3_VIEW, 0, 0},
{R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
{R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028D2C_CB_COLOR3_DIM, 0, 0},
{R_028D30_CB_COLOR3_CMASK, REG_FLAG_NEED_BO},
{R_028D34_CB_COLOR3_CMASK_SLICE},
{R_028D38_CB_COLOR3_FMASK, REG_FLAG_NEED_BO},
{R_028D3C_CB_COLOR3_FMASK_SLICE},
{R_028D40_CB_COLOR3_CLEAR_WORD0},
{R_028D44_CB_COLOR3_CLEAR_WORD1},
{R_028D48_CB_COLOR3_CLEAR_WORD2},
{R_028D4C_CB_COLOR3_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0},
{R_028D54_CB_COLOR4_PITCH, 0, 0},
{R_028D58_CB_COLOR4_SLICE, 0, 0},
{R_028D5C_CB_COLOR4_VIEW, 0, 0},
{R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
{R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028D68_CB_COLOR4_DIM, 0, 0},
{R_028D6C_CB_COLOR4_CMASK, REG_FLAG_NEED_BO},
{R_028D70_CB_COLOR4_CMASK_SLICE},
{R_028D74_CB_COLOR4_FMASK, REG_FLAG_NEED_BO},
{R_028D78_CB_COLOR4_FMASK_SLICE},
{R_028D7C_CB_COLOR4_CLEAR_WORD0},
{R_028D80_CB_COLOR4_CLEAR_WORD1},
{R_028D84_CB_COLOR4_CLEAR_WORD2},
{R_028D88_CB_COLOR4_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0},
{R_028D90_CB_COLOR5_PITCH, 0, 0},
{R_028D94_CB_COLOR5_SLICE, 0, 0},
{R_028D98_CB_COLOR5_VIEW, 0, 0},
{R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
{R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028DA4_CB_COLOR5_DIM, 0, 0},
{R_028DA8_CB_COLOR5_CMASK, REG_FLAG_NEED_BO},
{R_028DAC_CB_COLOR5_CMASK_SLICE},
{R_028DB0_CB_COLOR5_FMASK, REG_FLAG_NEED_BO},
{R_028DB4_CB_COLOR5_FMASK_SLICE},
{R_028DB8_CB_COLOR5_CLEAR_WORD0},
{R_028DBC_CB_COLOR5_CLEAR_WORD1},
{R_028DC0_CB_COLOR5_CLEAR_WORD2},
{R_028DC4_CB_COLOR5_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0},
{R_028DCC_CB_COLOR6_PITCH, 0, 0},
{R_028DD0_CB_COLOR6_SLICE, 0, 0},
{R_028DD4_CB_COLOR6_VIEW, 0, 0},
{R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
{R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028DE0_CB_COLOR6_DIM, 0, 0},
{R_028DE4_CB_COLOR6_CMASK, REG_FLAG_NEED_BO},
{R_028DE8_CB_COLOR6_CMASK_SLICE},
{R_028DEC_CB_COLOR6_FMASK, REG_FLAG_NEED_BO},
{R_028DF0_CB_COLOR6_FMASK_SLICE},
{R_028DF4_CB_COLOR6_CLEAR_WORD0},
{R_028DF8_CB_COLOR6_CLEAR_WORD1},
{R_028DFC_CB_COLOR6_CLEAR_WORD2},
{R_028E00_CB_COLOR6_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0},
{R_028E08_CB_COLOR7_PITCH, 0, 0},
{R_028E0C_CB_COLOR7_SLICE, 0, 0},
{R_028E10_CB_COLOR7_VIEW, 0, 0},
{R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
{R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028E1C_CB_COLOR7_DIM, 0, 0},
{R_028E20_CB_COLOR7_CMASK, REG_FLAG_NEED_BO},
{R_028E24_CB_COLOR7_CMASK_SLICE},
{R_028E28_CB_COLOR7_FMASK, REG_FLAG_NEED_BO},
{R_028E2C_CB_COLOR7_FMASK_SLICE},
{R_028E30_CB_COLOR7_CLEAR_WORD0},
{R_028E34_CB_COLOR7_CLEAR_WORD1},
{R_028E38_CB_COLOR7_CLEAR_WORD2},
{R_028E3C_CB_COLOR7_CLEAR_WORD3},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0},
{R_028E44_CB_COLOR8_PITCH, 0, 0},
{R_028E48_CB_COLOR8_SLICE, 0, 0},
{R_028E4C_CB_COLOR8_VIEW, 0, 0},
{R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0},
{R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028E58_CB_COLOR8_DIM, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0},
{R_028E60_CB_COLOR9_PITCH, 0, 0},
{R_028E64_CB_COLOR9_SLICE, 0, 0},
{R_028E68_CB_COLOR9_VIEW, 0, 0},
{R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0},
{R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028E74_CB_COLOR9_DIM, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0},
{R_028E7C_CB_COLOR10_PITCH, 0, 0},
{R_028E80_CB_COLOR10_SLICE, 0, 0},
{R_028E84_CB_COLOR10_VIEW, 0, 0},
{R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0},
{R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028E90_CB_COLOR10_DIM, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0},
{R_028E98_CB_COLOR11_PITCH, 0, 0},
{R_028E9C_CB_COLOR11_SLICE, 0, 0},
{R_028EA0_CB_COLOR11_VIEW, 0, 0},
{R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0},
{R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0},
{R_028EAC_CB_COLOR11_DIM, 0, 0},
};
static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)

577
src/gallium/drivers/r600/evergreen_state.c
View file

@ -1442,13 +1442,150 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
surf->depth_initialized = true;
}
static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
const struct pipe_framebuffer_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_surface *surf;
struct r600_texture *rtex;
uint32_t i, log_samples;
if (rctx->framebuffer.state.nr_cbufs) {
rctx->flags |= R600_CONTEXT_CB_FLUSH;
}
if (rctx->framebuffer.state.zsbuf) {
rctx->flags |= R600_CONTEXT_DB_FLUSH;
}
util_copy_framebuffer_state(&rctx->framebuffer.state, state);
/* Colorbuffers. */
rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
util_format_is_pure_integer(state->cbufs[0]->format);
rctx->framebuffer.compressed_cb_mask = 0;
if (state->nr_cbufs)
rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
else if (state->zsbuf)
rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
else
rctx->framebuffer.nr_samples = 0;
for (i = 0; i < state->nr_cbufs; i++) {
surf = (struct r600_surface*)state->cbufs[i];
rtex = (struct r600_texture*)surf->base.texture;
if (!surf->color_initialized) {
evergreen_init_color_surface(rctx, surf);
}
if (!surf->export_16bpc) {
rctx->framebuffer.export_16bpc = false;
}
/* Cayman can fetch from a compressed MSAA colorbuffer,
* so it's pointless to track them. */
if (rctx->chip_class != CAYMAN && rtex->fmask_size && rtex->cmask_size) {
rctx->framebuffer.compressed_cb_mask |= 1 << i;
}
}
/* Update alpha-test state dependencies.
* Alpha-test is done on the first colorbuffer only. */
if (state->nr_cbufs) {
surf = (struct r600_surface*)state->cbufs[0];
if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
rctx->alphatest_state.bypass = surf->alphatest_bypass;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
}
/* ZS buffer. */
if (state->zsbuf) {
surf = (struct r600_surface*)state->zsbuf;
if (!surf->depth_initialized) {
evergreen_init_depth_surface(rctx, surf);
}
evergreen_polygon_offset_update(rctx);
}
if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
rctx->alphatest_state.bypass = false;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
log_samples = util_logbase2(rctx->framebuffer.nr_samples);
if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
rctx->db_misc_state.log_samples = log_samples;
r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
}
/* Calculate the CS size. */
rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
/* MSAA. */
if (rctx->chip_class == EVERGREEN) {
switch (rctx->framebuffer.nr_samples) {
case 2:
case 4:
rctx->framebuffer.atom.num_dw += 6;
break;
case 8:
rctx->framebuffer.atom.num_dw += 10;
break;
}
rctx->framebuffer.atom.num_dw += 4;
} else {
switch (rctx->framebuffer.nr_samples) {
case 2:
case 4:
rctx->framebuffer.atom.num_dw += 12;
break;
case 8:
rctx->framebuffer.atom.num_dw += 16;
break;
case 16:
rctx->framebuffer.atom.num_dw += 18;
break;
}
rctx->framebuffer.atom.num_dw += 7;
}
/* Colorbuffers. */
rctx->framebuffer.atom.num_dw += state->nr_cbufs * 21;
if (rctx->keep_tiling_flags)
rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
/* ZS buffer. */
if (state->zsbuf) {
rctx->framebuffer.atom.num_dw += 21;
if (rctx->keep_tiling_flags)
rctx->framebuffer.atom.num_dw += 2;
}
r600_atom_dirty(rctx, &rctx->framebuffer.atom);
}
#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
(((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
(((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
(((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
(((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
static uint32_t evergreen_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
{
/* 2xMSAA
* There are two locations (-4, 4), (4, -4). */
@ -1480,35 +1617,45 @@ static uint32_t evergreen_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_
FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
};
static unsigned max_dist_8x = 8;
struct r600_context *rctx = (struct r600_context *)ctx;
unsigned i;
switch (nsample) {
case 2:
for (i = 0; i < Elements(sample_locs_2x); i++) {
r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
sample_locs_2x[i]);
}
return max_dist_2x;
case 4:
for (i = 0; i < Elements(sample_locs_4x); i++) {
r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
sample_locs_4x[i]);
}
return max_dist_4x;
case 8:
for (i = 0; i < Elements(sample_locs_8x); i++) {
r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
sample_locs_8x[i]);
}
return max_dist_8x;
struct radeon_winsys_cs *cs = rctx->cs;
unsigned max_dist = 0;
switch (nr_samples) {
default:
R600_ERR("Invalid nr_samples %i\n", nsample);
return 0;
nr_samples = 0;
break;
case 2:
r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_2x));
r600_write_array(cs, Elements(sample_locs_2x), sample_locs_2x);
max_dist = max_dist_2x;
break;
case 4:
r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_4x));
r600_write_array(cs, Elements(sample_locs_4x), sample_locs_4x);
max_dist = max_dist_4x;
break;
case 8:
r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
r600_write_array(cs, Elements(sample_locs_8x), sample_locs_8x);
max_dist = max_dist_8x;
break;
}
if (nr_samples > 1) {
r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
} else {
r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
}
}
static uint32_t cayman_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
{
/* 2xMSAA
* There are two locations (-4, 4), (4, -4). */
@ -1560,265 +1707,214 @@ static uint32_t cayman_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_sta
FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
};
static unsigned max_dist_16x = 8;
struct r600_context *rctx = (struct r600_context *)ctx;
uint32_t max_dist, num_regs, *sample_locs;
switch (nsample) {
struct radeon_winsys_cs *cs = rctx->cs;
unsigned max_dist = 0;
switch (nr_samples) {
default:
nr_samples = 0;
break;
case 2:
sample_locs = sample_locs_2x;
num_regs = Elements(sample_locs_2x);
r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
max_dist = max_dist_2x;
break;
case 4:
sample_locs = sample_locs_4x;
num_regs = Elements(sample_locs_4x);
r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
max_dist = max_dist_4x;
break;
case 8:
sample_locs = sample_locs_8x;
num_regs = Elements(sample_locs_8x);
r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
r600_write_value(cs, sample_locs_8x[0]);
r600_write_value(cs, sample_locs_8x[4]);
r600_write_value(cs, 0);
r600_write_value(cs, 0);
r600_write_value(cs, sample_locs_8x[1]);
r600_write_value(cs, sample_locs_8x[5]);
r600_write_value(cs, 0);
r600_write_value(cs, 0);
r600_write_value(cs, sample_locs_8x[2]);
r600_write_value(cs, sample_locs_8x[6]);
r600_write_value(cs, 0);
r600_write_value(cs, 0);
r600_write_value(cs, sample_locs_8x[3]);
r600_write_value(cs, sample_locs_8x[7]);
max_dist = max_dist_8x;
break;
case 16:
sample_locs = sample_locs_16x;
num_regs = Elements(sample_locs_16x);
r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
r600_write_value(cs, sample_locs_16x[0]);
r600_write_value(cs, sample_locs_16x[4]);
r600_write_value(cs, sample_locs_16x[8]);
r600_write_value(cs, sample_locs_16x[12]);
r600_write_value(cs, sample_locs_16x[1]);
r600_write_value(cs, sample_locs_16x[5]);
r600_write_value(cs, sample_locs_16x[9]);
r600_write_value(cs, sample_locs_16x[13]);
r600_write_value(cs, sample_locs_16x[2]);
r600_write_value(cs, sample_locs_16x[6]);
r600_write_value(cs, sample_locs_16x[10]);
r600_write_value(cs, sample_locs_16x[14]);
r600_write_value(cs, sample_locs_16x[3]);
r600_write_value(cs, sample_locs_16x[7]);
r600_write_value(cs, sample_locs_16x[11]);
r600_write_value(cs, sample_locs_16x[15]);
max_dist = max_dist_16x;
break;
default:
R600_ERR("Invalid nr_samples %i\n", nsample);
return 0;
}
r600_pipe_state_add_reg(rstate, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs[0]);
r600_pipe_state_add_reg(rstate, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs[1]);
r600_pipe_state_add_reg(rstate, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs[2]);
r600_pipe_state_add_reg(rstate, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs[3]);
if (num_regs <= 8) {
r600_pipe_state_add_reg(rstate, CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs[4]);
r600_pipe_state_add_reg(rstate, CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs[5]);
r600_pipe_state_add_reg(rstate, CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs[6]);
r600_pipe_state_add_reg(rstate, CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs[7]);
if (nr_samples > 1) {
unsigned log_samples = util_logbase2(nr_samples);
r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
r600_write_value(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(max_dist) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
S_028804_PS_ITER_SAMPLES(log_samples) |
S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
} else {
r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
r600_write_value(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
}
if (num_regs <= 16) {
r600_pipe_state_add_reg(rstate, CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, sample_locs[8]);
r600_pipe_state_add_reg(rstate, CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, sample_locs[9]);
r600_pipe_state_add_reg(rstate, CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, sample_locs[10]);
r600_pipe_state_add_reg(rstate, CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, sample_locs[11]);
r600_pipe_state_add_reg(rstate, CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, sample_locs[12]);
r600_pipe_state_add_reg(rstate, CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, sample_locs[13]);
r600_pipe_state_add_reg(rstate, CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, sample_locs[14]);
r600_pipe_state_add_reg(rstate, CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, sample_locs[15]);
}
return max_dist;
}
static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
const struct pipe_framebuffer_state *state)
static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
struct r600_surface *surf;
struct r600_resource *res;
struct r600_texture *rtex;
uint32_t tl, br, i, nr_samples, log_samples;
struct radeon_winsys_cs *cs = rctx->cs;
struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
unsigned nr_cbufs = state->nr_cbufs;
unsigned i, tl, br;
if (rstate == NULL)
return;
if (rctx->framebuffer.nr_cbufs) {
rctx->flags |= R600_CONTEXT_CB_FLUSH;
}
if (rctx->framebuffer.zsbuf) {
rctx->flags |= R600_CONTEXT_DB_FLUSH;
}
/* unreference old buffer and reference new one */
rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
util_copy_framebuffer_state(&rctx->framebuffer, state);
/* XXX support more colorbuffers once we need them */
assert(nr_cbufs <= 8);
if (nr_cbufs > 8)
nr_cbufs = 8;
/* Colorbuffers. */
rctx->export_16bpc = true;
rctx->nr_cbufs = state->nr_cbufs;
rctx->cb0_is_integer = state->nr_cbufs &&
util_format_is_pure_integer(state->cbufs[0]->format);
rctx->compressed_cb_mask = 0;
for (i = 0; i < nr_cbufs; i++) {
struct r600_surface *cb = (struct r600_surface*)state->cbufs[i];
unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)cb->base.texture,
RADEON_USAGE_READWRITE);
for (i = 0; i < state->nr_cbufs; i++) {
surf = (struct r600_surface*)state->cbufs[i];
res = (struct r600_resource*)surf->base.texture;
rtex = (struct r600_texture*)res;
r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 11);
r600_write_value(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
r600_write_value(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
r600_write_value(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
r600_write_value(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
r600_write_value(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
r600_write_value(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
r600_write_value(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
r600_write_value(cs, cb->cb_color_cmask); /* R_028C7C_CB_COLOR0_CMASK */
r600_write_value(cs, cb->cb_color_cmask_slice); /* R_028C80_CB_COLOR0_CMASK_SLICE */
r600_write_value(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
r600_write_value(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
if (!surf->color_initialized) {
evergreen_init_color_surface(rctx, surf);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
r600_write_value(cs, reloc);
if (!rctx->keep_tiling_flags) {
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
r600_write_value(cs, reloc);
}
if (!surf->export_16bpc) {
rctx->export_16bpc = false;
}
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
r600_write_value(cs, reloc);
r600_pipe_state_add_reg_bo(rstate, R_028C60_CB_COLOR0_BASE + i * 0x3C,
surf->cb_color_base, res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028C78_CB_COLOR0_DIM + i * 0x3C,
surf->cb_color_dim);
r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C,
surf->cb_color_info, res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028C64_CB_COLOR0_PITCH + i * 0x3C,
surf->cb_color_pitch);
r600_pipe_state_add_reg(rstate, R_028C68_CB_COLOR0_SLICE + i * 0x3C,
surf->cb_color_slice);
r600_pipe_state_add_reg(rstate, R_028C6C_CB_COLOR0_VIEW + i * 0x3C,
surf->cb_color_view);
r600_pipe_state_add_reg_bo(rstate, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C,
surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg_bo(rstate, R_028C7C_CB_COLOR0_CMASK + i * 0x3c,
surf->cb_color_cmask, res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028C80_CB_COLOR0_CMASK_SLICE + i * 0x3c,
surf->cb_color_cmask_slice);
r600_pipe_state_add_reg_bo(rstate, R_028C84_CB_COLOR0_FMASK + i * 0x3c,
surf->cb_color_fmask, res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028C88_CB_COLOR0_FMASK_SLICE + i * 0x3c,
surf->cb_color_fmask_slice);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
r600_write_value(cs, reloc);
/* Cayman can fetch from a compressed MSAA colorbuffer,
* so it's pointless to track them. */
if (rctx->chip_class != CAYMAN && rtex->fmask_size && rtex->cmask_size) {
rctx->compressed_cb_mask |= 1 << i;
}
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
r600_write_value(cs, reloc);
}
/* set CB_COLOR1_INFO for possible dual-src blending */
if (i == 1 && !((struct r600_texture*)res)->is_rat) {
r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
surf->cb_color_info, res, RADEON_USAGE_READWRITE);
if (i == 1 && !((struct r600_texture*)state->cbufs[0]->texture)->is_rat) {
r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
((struct r600_surface*)state->cbufs[0])->cb_color_info);
if (!rctx->keep_tiling_flags) {
unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->cbufs[0]->texture,
RADEON_USAGE_READWRITE);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
r600_write_value(cs, reloc);
}
i++;
}
for (; i < 8 ; i++) {
r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
}
/* Update alpha-test state dependencies.
* Alpha-test is done on the first colorbuffer only. */
if (state->nr_cbufs) {
surf = (struct r600_surface*)state->cbufs[0];
if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
rctx->alphatest_state.bypass = surf->alphatest_bypass;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
if (rctx->keep_tiling_flags) {
for (; i < 8 ; i++) {
r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
}
if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
for (; i < 12; i++) {
r600_write_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
}
}
/* ZS buffer. */
if (state->zsbuf) {
surf = (struct r600_surface*)state->zsbuf;
res = (struct r600_resource*)surf->base.texture;
struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
unsigned reloc = r600_context_bo_reloc(rctx, (struct r600_resource*)state->zsbuf->texture,
RADEON_USAGE_READWRITE);
if (!surf->depth_initialized) {
evergreen_init_depth_surface(rctx, surf);
r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
r600_write_value(cs, zb->db_depth_info); /* R_028040_DB_Z_INFO */
r600_write_value(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
r600_write_value(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
r600_write_value(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
r600_write_value(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
r600_write_value(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
r600_write_value(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
r600_write_value(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
if (!rctx->keep_tiling_flags) {
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
r600_write_value(cs, reloc);
}
r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
r600_write_value(cs, reloc);
r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
res, RADEON_USAGE_READWRITE);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
r600_write_value(cs, reloc);
r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
r600_write_value(cs, reloc);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
r600_write_value(cs, reloc);
}
/* Framebuffer dimensions. */
evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
r600_pipe_state_add_reg(rstate,
R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
r600_pipe_state_add_reg(rstate,
R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
r600_write_value(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
r600_write_value(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
/* Multisampling */
if (state->nr_cbufs)
nr_samples = state->cbufs[0]->texture->nr_samples;
else if (state->zsbuf)
nr_samples = state->zsbuf->texture->nr_samples;
else
nr_samples = 0;
if (nr_samples > 1) {
unsigned line_cntl = S_028C00_LAST_PIXEL(1) |
S_028C00_EXPAND_LINE_WIDTH(1);
log_samples = util_logbase2(nr_samples);
if (rctx->chip_class == CAYMAN) {
unsigned max_dist = cayman_set_ms_pos(ctx, rstate, nr_samples);
r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, line_cntl);
r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(max_dist) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
S_028804_PS_ITER_SAMPLES(log_samples) |
S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
} else {
unsigned max_dist = evergreen_set_ms_pos(ctx, rstate, nr_samples);
r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, line_cntl);
r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
S_028C04_MSAA_NUM_SAMPLES(log_samples) |
S_028C04_MAX_SAMPLE_DIST(max_dist));
}
if (rctx->chip_class == EVERGREEN) {
evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
} else {
log_samples = 0;
if (rctx->chip_class == CAYMAN) {
r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG, 0);
r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
} else {
r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
}
}
free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
r600_context_pipe_state_set(rctx, rstate);
if (state->zsbuf) {
evergreen_polygon_offset_update(rctx);
}
if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
rctx->alphatest_state.bypass = false;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
rctx->db_misc_state.log_samples = log_samples;
r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
cayman_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
}
}
@ -2126,6 +2222,7 @@ void evergreen_init_state_functions(struct r600_context *rctx)
* !!!
*/
r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
/* shader const */
r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
@ -2880,11 +2977,11 @@ void evergreen_polygon_offset_update(struct r600_context *rctx)
state.id = R600_PIPE_STATE_POLYGON_OFFSET;
state.nregs = 0;
if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
if (rctx->rasterizer && rctx->framebuffer.state.zsbuf) {
float offset_units = rctx->rasterizer->offset_units;
unsigned offset_db_fmt_cntl = 0, depth;
switch (rctx->framebuffer.zsbuf->format) {
switch (rctx->framebuffer.state.zsbuf->format) {
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
depth = -24;
@ -3169,16 +3266,16 @@ void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
void evergreen_update_dual_export_state(struct r600_context * rctx)
{
unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
!rctx->ps_shader->current->ps_depth_export;
bool dual_export = rctx->framebuffer.export_16bpc &&
!rctx->ps_shader->current->ps_depth_export;
unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
V_02880C_EXPORT_DB_FULL;
V_02880C_EXPORT_DB_FULL;
unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
S_02880C_DB_SOURCE_FORMAT(db_source_format) |
S_02880C_ALPHA_TO_MASK_DISABLE(rctx->cb0_is_integer);
S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
if (db_shader_control != rctx->db_shader_control) {
struct r600_pipe_state rstate;

4
src/gallium/drivers/r600/r600_blit.c
View file

@ -71,7 +71,7 @@ static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op
}
if (op & R600_SAVE_FRAMEBUFFER)
util_blitter_save_framebuffer(rctx->blitter, &rctx->framebuffer);
util_blitter_save_framebuffer(rctx->blitter, &rctx->framebuffer.state);
if (op & R600_SAVE_TEXTURES) {
util_blitter_save_fragment_sampler_states(
@ -509,7 +509,7 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers,
double depth, unsigned stencil)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct pipe_framebuffer_state *fb = &rctx->framebuffer;
struct pipe_framebuffer_state *fb = &rctx->framebuffer.state;
r600_blitter_begin(ctx, R600_CLEAR);
util_blitter_clear(rctx->blitter, fb->width, fb->height,

104
src/gallium/drivers/r600/r600_hw_context.c
View file

@ -226,99 +226,12 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
/* R600/R700 configuration */
static const struct r600_reg r600_config_reg_list[] = {
{R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, 0, 0},
{R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, 0, 0},
{R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 0, 0},
{R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, 0, 0},
{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
};
static const struct r600_reg r600_context_reg_list[] = {
{R_028A4C_PA_SC_MODE_CNTL, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
{R_028060_CB_COLOR0_SIZE, 0, 0},
{R_028080_CB_COLOR0_VIEW, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028100_CB_COLOR0_MASK, 0, 0},
{R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
{R_028064_CB_COLOR1_SIZE, 0, 0},
{R_028084_CB_COLOR1_VIEW, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0},
{R_028104_CB_COLOR1_MASK, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
{R_028068_CB_COLOR2_SIZE, 0, 0},
{R_028088_CB_COLOR2_VIEW, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0},
{R_028108_CB_COLOR2_MASK, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
{R_02806C_CB_COLOR3_SIZE, 0, 0},
{R_02808C_CB_COLOR3_VIEW, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0},
{R_02810C_CB_COLOR3_MASK, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
{R_028070_CB_COLOR4_SIZE, 0, 0},
{R_028090_CB_COLOR4_VIEW, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0},
{R_028110_CB_COLOR4_MASK, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
{R_028074_CB_COLOR5_SIZE, 0, 0},
{R_028094_CB_COLOR5_VIEW, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0},
{R_028114_CB_COLOR5_MASK, 0, 0},
{R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)},
{R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
{R_028078_CB_COLOR6_SIZE, 0, 0},
{R_028098_CB_COLOR6_VIEW, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0},
{R_028118_CB_COLOR6_MASK, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
{R_02807C_CB_COLOR7_SIZE, 0, 0},
{R_02809C_CB_COLOR7_VIEW, 0, 0},
{R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0},
{R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0},
{R_02811C_CB_COLOR7_MASK, 0, 0},
{R_028120_CB_CLEAR_RED, 0, 0},
{R_028124_CB_CLEAR_GREEN, 0, 0},
{R_028128_CB_CLEAR_BLUE, 0, 0},
@ -334,20 +247,12 @@ static const struct r600_reg r600_context_reg_list[] = {
{R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0},
{R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0},
{R_0287A0_CB_SHADER_CONTROL, 0, 0},
{R_028800_DB_DEPTH_CONTROL, 0, 0},
{R_028804_CB_BLEND_CONTROL, 0, 0},
{R_02880C_DB_SHADER_CONTROL, 0, 0},
{R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH},
{R_028000_DB_DEPTH_SIZE, 0, 0},
{R_028004_DB_DEPTH_VIEW, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0},
{R_028D24_DB_HTILE_SURFACE, 0, 0},
{R_028D34_DB_PREFETCH_LIMIT, 0, 0},
{R_028D44_DB_ALPHA_TO_MASK, 0, 0},
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
@ -355,8 +260,6 @@ static const struct r600_reg r600_context_reg_list[] = {
{R_028A00_PA_SU_POINT_SIZE, 0, 0},
{R_028A04_PA_SU_POINT_MINMAX, 0, 0},
{R_028A08_PA_SU_LINE_CNTL, 0, 0},
{R_028C00_PA_SC_LINE_CNTL, 0, 0},
{R_028C04_PA_SC_AA_CONFIG, 0, 0},
{R_028C08_PA_SU_VTX_CNTL, 0, 0},
{R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
{R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
@ -457,8 +360,6 @@ static const struct r600_reg r600_context_reg_list[] = {
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
{R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
{R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0},
{R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0},
};
static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)
@ -980,7 +881,9 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
}
/* force to keep tiling flags */
flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
if (ctx->keep_tiling_flags) {
flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
}
/* Flush the CS. */
ctx->ws->cs_flush(ctx->cs, flags);
@ -1006,6 +909,7 @@ void r600_begin_new_cs(struct r600_context *ctx)
r600_atom_dirty(ctx, &ctx->clip_misc_state.atom);
r600_atom_dirty(ctx, &ctx->clip_state.atom);
r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
r600_atom_dirty(ctx, &ctx->framebuffer.atom);
r600_atom_dirty(ctx, &ctx->vgt_state.atom);
r600_atom_dirty(ctx, &ctx->vgt2_state.atom);
r600_atom_dirty(ctx, &ctx->sample_mask.atom);

3
src/gallium/drivers/r600/r600_pipe.c
View file

@ -174,7 +174,7 @@ static void r600_destroy_context(struct pipe_context *context)
if (rctx->custom_blend_decompress) {
rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress);
}
util_unreference_framebuffer_state(&rctx->framebuffer);
util_unreference_framebuffer_state(&rctx->framebuffer.state);
r600_context_fini(rctx);
@ -223,6 +223,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
rctx->ws = rscreen->ws;
rctx->family = rscreen->family;
rctx->chip_class = rscreen->chip_class;
rctx->keep_tiling_flags = rscreen->info.drm_minor >= 12;
LIST_INITHEAD(&rctx->active_timer_queries);
LIST_INITHEAD(&rctx->active_nontimer_queries);

20
src/gallium/drivers/r600/r600_pipe.h
View file

@ -35,7 +35,7 @@
#include "r600_resource.h"
#include "evergreen_compute.h"
#define R600_NUM_ATOMS 28
#define R600_NUM_ATOMS 29
#define R600_MAX_CONST_BUFFERS 2
#define R600_MAX_CONST_BUFFER_SIZE 4096
@ -126,6 +126,16 @@ struct r600_cs_shader_state {
struct r600_pipe_compute *shader;
};
struct r600_framebuffer {
struct r600_atom atom;
struct pipe_framebuffer_state state;
unsigned compressed_cb_mask;
unsigned nr_samples;
bool export_16bpc;
bool cb0_is_integer;
bool is_msaa_resolve;
};
struct r600_sample_mask {
struct r600_atom atom;
uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
@ -153,7 +163,6 @@ enum r600_pipe_state_id {
R600_PIPE_STATE_BLEND = 0,
R600_PIPE_STATE_SCISSOR,
R600_PIPE_STATE_RASTERIZER,
R600_PIPE_STATE_FRAMEBUFFER,
R600_PIPE_STATE_DSA,
R600_PIPE_STATE_POLYGON_OFFSET,
R600_PIPE_STATE_FETCH_SHADER,
@ -355,6 +364,7 @@ struct r600_context {
enum radeon_family family;
enum chip_class chip_class;
boolean has_vertex_cache;
boolean keep_tiling_flags;
unsigned r6xx_num_clause_temp_gprs;
void *custom_dsa_flush;
void *custom_blend_resolve;
@ -364,8 +374,6 @@ struct r600_context {
struct radeon_winsys *ws;
struct r600_pipe_state *states[R600_PIPE_NSTATES];
struct r600_vertex_element *vertex_elements;
struct pipe_framebuffer_state framebuffer;
unsigned compressed_cb_mask;
unsigned compute_cb_target_mask;
unsigned db_shader_control;
unsigned pa_sc_line_stipple;
@ -383,11 +391,8 @@ struct r600_context {
boolean spi_dirty;
unsigned sprite_coord_enable;
boolean flatshade;
boolean export_16bpc;
unsigned nr_cbufs;
bool alpha_to_one;
bool multisample_enable;
bool cb0_is_integer;
struct u_upload_mgr *uploader;
struct util_slab_mempool pool_transfers;
@ -409,6 +414,7 @@ struct r600_context {
struct r600_clip_misc_state clip_misc_state;
struct r600_clip_state clip_state;
struct r600_db_misc_state db_misc_state;
struct r600_framebuffer framebuffer;
struct r600_seamless_cube_map seamless_cube_map;
struct r600_stencil_ref_state stencil_ref;
struct r600_vgt_state vgt_state;

466
src/gallium/drivers/r600/r600_state.c
View file

@ -647,11 +647,11 @@ void r600_polygon_offset_update(struct r600_context *rctx)
state.id = R600_PIPE_STATE_POLYGON_OFFSET;
state.nregs = 0;
if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
if (rctx->rasterizer && rctx->framebuffer.state.zsbuf) {
float offset_units = rctx->rasterizer->offset_units;
unsigned offset_db_fmt_cntl = 0, depth;
switch (rctx->framebuffer.zsbuf->format) {
switch (rctx->framebuffer.state.zsbuf->format) {
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
depth = -24;
@ -1446,13 +1446,127 @@ static void r600_init_depth_surface(struct r600_context *rctx,
surf->depth_initialized = true;
}
static void r600_set_framebuffer_state(struct pipe_context *ctx,
const struct pipe_framebuffer_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_surface *surf;
struct r600_texture *rtex;
unsigned i;
if (rctx->framebuffer.state.nr_cbufs) {
rctx->flags |= R600_CONTEXT_CB_FLUSH;
}
if (rctx->framebuffer.state.zsbuf) {
rctx->flags |= R600_CONTEXT_DB_FLUSH;
}
/* R6xx errata */
if (rctx->chip_class == R600) {
rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
}
/* Set the new state. */
util_copy_framebuffer_state(&rctx->framebuffer.state, state);
rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
util_format_is_pure_integer(state->cbufs[0]->format);
rctx->framebuffer.compressed_cb_mask = 0;
rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
state->cbufs[0]->texture->nr_samples > 1 &&
state->cbufs[1]->texture->nr_samples <= 1;
if (state->nr_cbufs)
rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
else if (state->zsbuf)
rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
else
rctx->framebuffer.nr_samples = 0;
/* Colorbuffers. */
for (i = 0; i < state->nr_cbufs; i++) {
/* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
bool force_cmask_fmask = rctx->chip_class == R600 &&
rctx->framebuffer.is_msaa_resolve &&
i == 1;
surf = (struct r600_surface*)state->cbufs[i];
rtex = (struct r600_texture*)surf->base.texture;
if (!surf->color_initialized || force_cmask_fmask) {
r600_init_color_surface(rctx, surf, force_cmask_fmask);
if (force_cmask_fmask) {
/* re-initialize later without compression */
surf->color_initialized = false;
}
}
if (!surf->export_16bpc) {
rctx->framebuffer.export_16bpc = false;
}
if (rtex->fmask_size && rtex->cmask_size) {
rctx->framebuffer.compressed_cb_mask |= 1 << i;
}
}
/* Update alpha-test state dependencies.
* Alpha-test is done on the first colorbuffer only. */
if (state->nr_cbufs) {
surf = (struct r600_surface*)state->cbufs[0];
if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
rctx->alphatest_state.bypass = surf->alphatest_bypass;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
}
/* ZS buffer. */
if (state->zsbuf) {
surf = (struct r600_surface*)state->zsbuf;
if (!surf->depth_initialized) {
r600_init_depth_surface(rctx, surf);
}
r600_polygon_offset_update(rctx);
}
if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
rctx->alphatest_state.bypass = false;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
/* Calculate the CS size. */
rctx->framebuffer.atom.num_dw =
10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
if (rctx->framebuffer.state.nr_cbufs) {
rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
}
if (rctx->framebuffer.state.zsbuf) {
rctx->framebuffer.atom.num_dw += 13;
}
if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
rctx->framebuffer.atom.num_dw += 2;
}
r600_atom_dirty(rctx, &rctx->framebuffer.atom);
}
#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
(((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
(((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
(((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
(((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
static uint32_t r600_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
{
static uint32_t sample_locs_2x[] = {
FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
@ -1469,229 +1583,202 @@ static uint32_t r600_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state
FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
};
static unsigned max_dist_8x = 8;
struct r600_context *rctx = (struct r600_context *)ctx;
struct radeon_winsys_cs *cs = rctx->cs;
unsigned max_dist = 0;
if (rctx->family == CHIP_R600) {
switch (nsample) {
case 0:
case 1:
return 0;
switch (nr_samples) {
default:
nr_samples = 0;
break;
case 2:
r600_pipe_state_add_reg(rstate, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
return max_dist_2x;
r600_write_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
max_dist = max_dist_2x;
break;
case 4:
r600_pipe_state_add_reg(rstate, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
return max_dist_4x;
r600_write_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
max_dist = max_dist_4x;
break;
case 8:
r600_pipe_state_add_reg(rstate, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, sample_locs_8x[0]);
r600_pipe_state_add_reg(rstate, R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, sample_locs_8x[1]);
return max_dist_8x;
r600_write_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
r600_write_value(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
r600_write_value(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
max_dist = max_dist_8x;
break;
}
} else {
switch (nsample) {
case 0:
case 1:
r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0);
r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, 0);
return 0;
switch (nr_samples) {
default:
r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
r600_write_value(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
r600_write_value(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
nr_samples = 0;
break;
case 2:
r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_2x[0]);
r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_2x[1]);
return max_dist_2x;
r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
r600_write_value(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
r600_write_value(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
max_dist = max_dist_2x;
break;
case 4:
r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_4x[0]);
r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_4x[1]);
return max_dist_4x;
r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
r600_write_value(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
r600_write_value(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
max_dist = max_dist_4x;
break;
case 8:
r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_8x[0]);
r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_8x[1]);
return max_dist_8x;
r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
r600_write_value(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
r600_write_value(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
max_dist = max_dist_8x;
break;
}
}
R600_ERR("Invalid nr_samples %i\n", nsample);
return 0;
if (nr_samples > 1) {
r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
} else {
r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
}
}
static void r600_set_framebuffer_state(struct pipe_context *ctx,
const struct pipe_framebuffer_state *state)
static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
struct r600_surface *surf;
struct r600_resource *res;
struct r600_texture *rtex;
uint32_t tl, br, i, nr_samples, max_dist;
bool is_resolve = state->nr_cbufs == 2 &&
state->cbufs[0]->texture->nr_samples > 1 &&
state->cbufs[1]->texture->nr_samples <= 1;
/* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
bool cb1_force_cmask_fmask = rctx->chip_class == R600 && is_resolve;
if (rstate == NULL)
return;
if (rctx->framebuffer.nr_cbufs) {
rctx->flags |= R600_CONTEXT_CB_FLUSH;
}
if (rctx->framebuffer.zsbuf) {
rctx->flags |= R600_CONTEXT_DB_FLUSH;
}
/* R6xx errata */
if (rctx->chip_class == R600) {
rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
}
/* unreference old buffer and reference new one */
rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
util_copy_framebuffer_state(&rctx->framebuffer, state);
struct radeon_winsys_cs *cs = rctx->cs;
struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
unsigned nr_cbufs = state->nr_cbufs;
struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
unsigned i, sbu = 0;
/* Colorbuffers. */
rctx->export_16bpc = true;
rctx->nr_cbufs = state->nr_cbufs;
rctx->cb0_is_integer = state->nr_cbufs &&
util_format_is_pure_integer(state->cbufs[0]->format);
rctx->compressed_cb_mask = 0;
for (i = 0; i < state->nr_cbufs; i++) {
bool force_cmask_fmask = cb1_force_cmask_fmask && i == 1;
surf = (struct r600_surface*)state->cbufs[i];
res = (struct r600_resource*)surf->base.texture;
rtex = (struct r600_texture*)res;
if (!surf->color_initialized || force_cmask_fmask) {
r600_init_color_surface(rctx, surf, force_cmask_fmask);
if (force_cmask_fmask) {
/* re-initialize later without compression */
surf->color_initialized = false;
}
}
if (!surf->export_16bpc) {
rctx->export_16bpc = false;
}
r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4,
surf->cb_color_base, res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4,
surf->cb_color_info, res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4,
surf->cb_color_size);
r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
surf->cb_color_view);
r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
surf->cb_color_fmask, surf->cb_buffer_fmask,
RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
surf->cb_color_cmask, surf->cb_buffer_cmask,
RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + i * 4,
surf->cb_color_mask);
if (rtex->fmask_size && rtex->cmask_size) {
rctx->compressed_cb_mask |= 1 << i;
}
r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
for (i = 0; i < nr_cbufs; i++) {
r600_write_value(cs, cb[i]->cb_color_info);
}
/* set CB_COLOR1_INFO for possible dual-src blending */
if (i == 1) {
r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4,
surf->cb_color_info, res, RADEON_USAGE_READWRITE);
r600_write_value(cs, cb[0]->cb_color_info);
i++;
}
for (; i < 8 ; i++) {
r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 0);
for (; i < 8; i++) {
r600_write_value(cs, 0);
}
/* Update alpha-test state dependencies.
* Alpha-test is done on the first colorbuffer only. */
if (state->nr_cbufs) {
surf = (struct r600_surface*)state->cbufs[0];
if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
rctx->alphatest_state.bypass = surf->alphatest_bypass;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
if (nr_cbufs) {
/* COLOR_BASE */
r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
for (i = 0; i < nr_cbufs; i++) {
r600_write_value(cs, cb[i]->cb_color_base);
}
/* relocations */
for (i = 0; i < nr_cbufs; i++) {
unsigned reloc = r600_context_bo_reloc(rctx,
(struct r600_resource*)cb[i]->base.texture,
RADEON_USAGE_READWRITE);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
r600_write_value(cs, reloc);
}
r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
for (i = 0; i < nr_cbufs; i++) {
r600_write_value(cs, cb[i]->cb_color_size);
}
r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
for (i = 0; i < nr_cbufs; i++) {
r600_write_value(cs, cb[i]->cb_color_view);
}
r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
for (i = 0; i < nr_cbufs; i++) {
r600_write_value(cs, cb[i]->cb_color_mask);
}
/* FMASK. */
r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
for (i = 0; i < nr_cbufs; i++) {
r600_write_value(cs, cb[i]->cb_color_fmask);
}
/* relocations */
for (i = 0; i < nr_cbufs; i++) {
unsigned reloc = r600_context_bo_reloc(rctx,
cb[i]->cb_buffer_fmask,
RADEON_USAGE_READWRITE);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
r600_write_value(cs, reloc);
}
/* CMASK. */
r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
for (i = 0; i < nr_cbufs; i++) {
r600_write_value(cs, cb[i]->cb_color_cmask);
}
/* relocations */
for (i = 0; i < nr_cbufs; i++) {
unsigned reloc = r600_context_bo_reloc(rctx,
cb[i]->cb_buffer_cmask,
RADEON_USAGE_READWRITE);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
r600_write_value(cs, reloc);
}
sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
}
/* ZS buffer. */
/* Zbuffer. */
if (state->zsbuf) {
surf = (struct r600_surface*)state->zsbuf;
res = (struct r600_resource*)surf->base.texture;
struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
unsigned reloc = r600_context_bo_reloc(rctx,
(struct r600_resource*)state->zsbuf->texture,
RADEON_USAGE_READWRITE);
if (!surf->depth_initialized) {
r600_init_depth_surface(rctx, surf);
}
r600_write_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
r600_write_value(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
r600_write_value(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
r600_write_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
r600_write_value(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
r600_write_value(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base,
res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size);
r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view);
r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info,
res, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
r600_write_value(cs, reloc);
r600_write_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
sbu |= SURFACE_BASE_UPDATE_DEPTH;
}
/* SURFACE_BASE_UPDATE */
if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770 && sbu) {
r600_write_value(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
r600_write_value(cs, sbu);
}
/* Framebuffer dimensions. */
tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
r600_write_value(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
r600_write_value(cs, S_028244_BR_X(state->width) |
S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
r600_pipe_state_add_reg(rstate,
R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
r600_pipe_state_add_reg(rstate,
R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
/* If we're doing MSAA resolve... */
if (is_resolve) {
r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1);
if (rctx->framebuffer.is_msaa_resolve) {
r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
} else {
/* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
* will assure that the alpha-test will work even if there is
* no colorbuffer bound. */
r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
(1ull << MAX2(state->nr_cbufs, 1)) - 1);
r600_write_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
(1ull << MAX2(nr_cbufs, 1)) - 1);
}
/* Multisampling */
if (state->nr_cbufs)
nr_samples = state->cbufs[0]->texture->nr_samples;
else if (state->zsbuf)
nr_samples = state->zsbuf->texture->nr_samples;
else
nr_samples = 0;
max_dist = r600_set_ms_pos(ctx, rstate, nr_samples);
if (nr_samples > 1) {
unsigned log_samples = util_logbase2(nr_samples);
r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL,
S_028C00_LAST_PIXEL(1) |
S_028C00_EXPAND_LINE_WIDTH(1));
r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
S_028C04_MSAA_NUM_SAMPLES(log_samples) |
S_028C04_MAX_SAMPLE_DIST(max_dist));
} else {
r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
}
free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
r600_context_pipe_state_set(rctx, rstate);
if (state->zsbuf) {
r600_polygon_offset_update(rctx);
}
if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
rctx->alphatest_state.bypass = false;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
}
static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
@ -2012,6 +2099,8 @@ void r600_init_state_functions(struct r600_context *rctx)
* !!!
*/
r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
/* shader const */
r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
@ -2687,8 +2776,9 @@ void *r600_create_db_flush_dsa(struct r600_context *rctx)
void r600_update_dual_export_state(struct r600_context * rctx)
{
unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
!rctx->ps_shader->current->ps_depth_export;
bool dual_export = rctx->framebuffer.export_16bpc &&
!rctx->ps_shader->current->ps_depth_export;
unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
S_02880C_DUAL_EXPORT_ENABLE(dual_export);

16
src/gallium/drivers/r600/r600_state_common.c
View file

@ -737,9 +737,11 @@ static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_contex
if (sel->type == PIPE_SHADER_FRAGMENT) {
key.color_two_side = rctx->two_side;
key.alpha_to_one = rctx->alpha_to_one && rctx->multisample_enable && !rctx->cb0_is_integer;
key.alpha_to_one = rctx->alpha_to_one &&
rctx->multisample_enable &&
!rctx->framebuffer.cb0_is_integer;
key.dual_src_blend = rctx->dual_src_blend;
key.nr_cbufs = rctx->nr_cbufs;
key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
}
return key;
}
@ -1316,20 +1318,20 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
}
/* Set the depth buffer as dirty. */
if (rctx->framebuffer.zsbuf) {
struct pipe_surface *surf = rctx->framebuffer.zsbuf;
if (rctx->framebuffer.state.zsbuf) {
struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
struct r600_texture *rtex = (struct r600_texture *)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
}
if (rctx->compressed_cb_mask) {
if (rctx->framebuffer.compressed_cb_mask) {
struct pipe_surface *surf;
struct r600_texture *rtex;
unsigned mask = rctx->compressed_cb_mask;
unsigned mask = rctx->framebuffer.compressed_cb_mask;
do {
unsigned i = u_bit_scan(&mask);
surf = rctx->framebuffer.cbufs[i];
surf = rctx->framebuffer.state.cbufs[i];
rtex = (struct r600_texture*)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;

1
src/gallium/drivers/r600/r600d.h
View file

@ -110,6 +110,7 @@
#define PKT3_SURFACE_BASE_UPDATE 0x73
#define SURFACE_BASE_UPDATE_DEPTH (1 << 0)
#define SURFACE_BASE_UPDATE_COLOR(x) (2 << (x))
#define SURFACE_BASE_UPDATE_COLOR_NUM(x) (((1 << x) - 1) << 1)
#define SURFACE_BASE_UPDATE_STRMOUT(x) (0x200 << (x))
#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10