Commit graph

92900 commits

Author SHA1 Message Date
Marek Olšák
c8b6f42e25 radeonsi: rename si_vertex_element -> si_vertex_elements
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
7be6186e0c radeonsi: allocate si_state_rasterizer::pm4_poly_offset only when needed
Each element has over 700 bytes.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
a828f5d783 radeonsi: pack si_state_rasterizer fields
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
6b6fed3a3c radeonsi: remove 8 bytes from si_shader_key with uint32_t ff_tcs_inputs_to_copy
The previous patch helps with this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
7b2240ac9c radeonsi: use uint32_t to declare si_shader_key.opt.kill_outputs
the next patch will benefit from this

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
1621b33d73 radeonsi: remove 8 bytes from si_shader_key by flattening opt.hw_vs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
30882ba0dd radeonsi: don't emit DB_STENCIL_CONTROL if it has no effect
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
6743dc01fd radeonsi: fix missing num_L2_invalidates increment
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
c503381864 radeonsi: get rid of more compressed_colortex_mask names
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
3d8259194d gallium/noop: fix sampler views
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
7448342a1f gallium/docs: clarify gen_name/get_vendor/get_device_vendor behavior
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
0d62e8a727 st/mesa: call check_program_state only when needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
9a22c85618 r600g: set pipe_context::priv = NULL
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101254

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Marek Olšák
e8be83f7f8 vl,omx,va,vdpau,xvmc: don't set the priv pointer in context_create
Unused and radeonsi ignores it anyway.

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 18:24:37 +02:00
Juan A. Suarez Romero
621a784529 r600/eg: distribute egd_tables.py in the dist file
Otherwise, `make distcheck` will fail.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-12 11:35:24 +02:00
Juan A. Suarez Romero
4152edbcde i965: include gen4_blorp_exec.h into EXTRA_DIST
Otherwise, `make distcheck` will fail.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-12 10:32:18 +02:00
Kenneth Graunke
b7153c3e9f i965: Call intel_prepare_render() from intel_update_state()
The resolve code looks at the current color draw buffers.  These are not
valid until intel_prepare_render() is called.  You can end up with one
color buffer bound, but where the renderbuffer has zero width/height and
no miptree allocated.

You can get a call chain like: _mesa_Clear -> _mesa_update_state ->
intel_update_state, where no brw driver hooks were called, so there is
no other point at which we could have called this.

Fixes crashes in KWin where Clear was causing intel_disable_rb_aux_buffer
to crash on irb != NULL but irb->mt == NULL.

According to Tapani, this also fixes crashes seen on Android.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
2017-06-12 01:10:36 -07:00
Grazvydas Ignotas
fae3b13905 radv: fix trace dumping for !use_ib_bos
Fixes trace dumping crash for SI or when RADV_DEBUG=noibs is set.

Fixes: 97dfff5410 "radv: Dump command buffer on hang."
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-06-11 23:07:09 +03:00
Grazvydas Ignotas
f56aa25ac5 radv: don't even attempt to prefetch on SI
Before bcae327469 this was emitting CP DMA packet even on SI, but
apparently hasn't caused too many problems. After that commit the
CP DMA code now always sets the CIK+ only bit for prefetch. Just
follow radeonsi there and don't try to prefetch at all.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101334
Fixes: bcae327469 "radv: realign cp dma code with radeonsi"
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-06-11 14:28:40 +03:00
Grazvydas Ignotas
f490200973 radv: assert on CP_DMA_USE_L2 for SI
The register header (and radeonsi comment) states V_411_SRC_ADDR_TC_L2
is for CIK+ only, so let's assert on earlier ASICs.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-06-11 14:28:08 +03:00
Harish Krupo
9827547313 egl/android: support for EGL_KHR_partial_update
This patch adds support for the EGL_KHR_partial_update extension for
android platform. It passes 36/37 tests in dEQP for EGL_KHR_partial_update.
1 test not supported.

v2: add fallback for eglSetDamageRegionKHR (Tapani)

v3: The native_window_set_surface_damage call is available only from
    Android version 6.0. Reintroduce the ANDROID_VERSION guard and
    advertise extension only if version is >= 6.0. (Emil Velikov)

v4: use newly introduced ANDROID_API_LEVEL guard rather than
    ANDROID_VERSION guard to advertise the extension.The extension
    is advertised only if ANDROID_API_LEVEL >= 23 (Android 6.0 or
    greater). Add fallback function for platforms other than Android.
    Fix possible math overflow. (Emil Velikov)
    Return immediately when n_rects is 0. Place function's entrypoint
    in alphabetical order. (Eric Engestrom)

v5: Replace unnecessary calloc with malloc (Eric)
    Check for BAD_ALLOC error (Emil)
    Check for error in native_window_set_damage_region. (Emil, Tapani,
    Eric).

Signed-off-by: Harish Krupo <harish.krupo.kps@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-06-11 01:02:09 +01:00
Marius Gräfe
f3c0bbe18a gallium: fixed modulo zero crashes in tgsi interpreter (v2)
softpipe throws integer division by zero exceptions on windows
when using % with integers in a geometry shader.

v2: Made error results consistent with existing div/mod zero handling in
    tgsi. 64 bit signed integer division by zero returns zero like in
    micro_idiv, unsigned returns ~0u like in micro_udiv.
    Modulo operations always set all result bits to one (like in
    micro_umod).

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-06-10 16:40:13 +02:00
Grazvydas Ignotas
29b9f35704 nir: make various getters take const pointers
This will allow to constify other things.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-06-10 16:48:45 +03:00
Ben Widawsky
e179a3438a i965/cnl: Add a preliminary device for Cannonlake
v2 (Anuj):
Rebased on master and updated pci ids
Remove redundant initialization of max_wm_threads to 64 * 12.
For gen9+ max_wm_threads are initialized in gen_get_device_info().

v3 (Anuj):
Move the patch to end of series.
Remove unused gt1, gt2, gt3 functions.
Remove l3_banks variable. Variable is now available on master.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-06-09 16:03:00 -07:00
Jason Ekstrand
f2cbf738b4 anv: Don't advertise support on anything above gen9
This will prevent the driver from even trying to work on Cannon Lake
until we get actual support added.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-06-09 16:03:00 -07:00
Anuj Phogat
9acc93feeb i965/cnl: Enable CCS_E and RT support for few formats
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:59 -07:00
Anuj Phogat
61f171292e i965/cnl: Reformat surface_format_info table to accomodate gen10+
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:59 -07:00
Anuj Phogat
f9e31a26d4 i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3
v1: By Ben Widawsky <benjamin.widawsky@intel.com>
v2: v1 had an assert only for VS. Add the restriction for GS, HS and
    DS as well and make sure the allocated sizes are not multiple of 3.
v3: Move the entry_size checks in to compiler code (Ken)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-09 16:02:59 -07:00
Anuj Phogat
b76659997e i965/cnl: Don't resolve single sampled color rb in case of sRGB formats
As sRGB now supports lossless compression, we also need to stop resolving
single sampled color render buffers for sRGB formats in Gen 10.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:59 -07:00
Ben Widawsky
640f5d3957 i965/cnl: Implement depth count workaround
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:59 -07:00
Anuj Phogat
8c43e33560 i965/cnl: Start using CNL MOCS defines
CNL MOCS defines are duplicates of SKL MOCS defines.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:59 -07:00
Anuj Phogat
111881abac i965/cnl: Handle gen10 in switch cases across the driver
V2: Start using gen10 functions isl_gen10*(), gen10_blorp_exec()
    gen10_init_atoms() (Jason)
    Remove Vulkan changes. Do them later in a separate patch.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:59 -07:00
Anuj Phogat
30e749c8f1 i965/cnl: Update few assertions
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:59 -07:00
Anuj Phogat
56b4d82729 i965/cnl: Add cnl bits in aubinator
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:58 -07:00
Anuj Phogat
dd6c27ace1 i965/cnl: Add pci id for INTEL_DEVID_OVERRIDE
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:58 -07:00
Anuj Phogat
dc83ce7a16 i965/cnl: Wire up android Mesa build files for gen10
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-06-09 16:02:58 -07:00
Anuj Phogat
e01c5a6824 i965/cnl: Wire up Mesa build files for gen10
V2: Remove isl_gen10.c and isl_gen10.h

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-09 16:02:58 -07:00
Anuj Phogat
2417d5ca19 intel/genxml: Update genx_bits for gen10+
This commit adds a gen10 case to the switch statement and
drops some unneeded code for handling gen numbers which
doesn't work on gen10 and above.

V2: Drop "z = float(z)" and the "z *= 10" lines

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:58 -07:00
Anuj Phogat
98b95a3735 i965/cnl: Add gen10 specific function declarations
These declarations will help the code start compiling
once we wire up the makefiles for gen10. Later patches
will start using these functions for gen10.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:58 -07:00
Anuj Phogat
2704ccc646 i965/cnl: Include gen10_pack.h
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:58 -07:00
Anuj Phogat
a48cb9cf7f i965/cnl: Define genX(x) and GENX(x) for gen10
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:58 -07:00
Jason Ekstrand
aa416f515a i965/genxml: Add gen10.xml
V2(Anuj):
Add default value for length of 3DPRIMITIVE command
Add values for 'Attribute Active Component Format'
Rename few fields to match gen9.xml

V3 (Ander Conselvan de Oliveira)
Add gen10 alias for MOCS
Make 3DSTATE_CONSTANT_BODY on Gen10 use arrays

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-06-09 16:00:49 -07:00
Ben Widawsky
d968f072bc i965: Make feature macros gen8 based
All the "features" of the hardware are similar starting with GEN8, so remove as
much of the GEN9 uniqueness as possible. This makes implementing future gen
platforms a bit easier.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 15:27:14 -07:00
Dave Airlie
51553c0bea radv: set fmask state to all 0s when no fmask. (v2)
The shader reads the descriptor to decide if it should take the
fmask value, however we weren't initing it always, which meant
random crap, esp with MSAA depth textures.

Fixes random hangs with:
dEQP-VK.glsl.builtin_var.fragdepth.*

v2: check fmask_state is not NULL

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-09 20:41:55 +01:00
Matt Turner
71651b3139 i965: Temporarily disable async mappings on non-LLC
Fixes regressions from commits e0a9b261e5 and a16355d67d by
neutering async mappings on non-LLC to be synchronous, like they were
before those two commits. :(

The failing tests include

piglit-test piglit.spec.nv_primitive_restart.primitive-restart-vbo_index_only
piglit-test piglit.spec.nv_primitive_restart.primitive-restart-vbo_combined_vertex_and_index
piglit-test piglit.spec.nv_primitive_restart.primitive-restart-vbo_separate_vertex_and_index
piglit-test piglit.spec.nv_primitive_restart.primitive-restart-vbo_vertex_only
piglit-test piglit.spec.arb_pixel_buffer_object.texsubimage-unpack pbo
2017-06-09 12:14:28 -07:00
Rafael Antognolli
d42fc65bb3 mesa/main/debug: Check if we successfully reopened the ppm file.
Since we created the file, we should be able to reopen it for appending, but
some weird filesystem error could cause that to be false. So simply check
whether we could reopen it or not.

CID: 1177144
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-06-09 10:21:16 -07:00
Brian Paul
81e15a5dea tgsi: clarify TGSI_SEMANTIC_SAMPLEMASK documentation
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-09 08:51:56 -06:00
Frank Richter
0ef39e588f gallium/wgl: Allow context creation even if SetPixelFormat() wasn't called
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101326
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-06-09 08:51:45 -06:00
Varad Gautam
f84bb6a9d9 st/dri: support format modifier queries
ask the driver for supported modifiers for a given format.

v2: move to __DRIimageExtension v16.
v3: fail if the supplied format is not supported by driver.
v4: purge PIPE_CAP_QUERY_DMABUF_ATTRIBS.
v5:
- move to __DRIimageExtension v15, pass external_only to the driver.

Signed-off-by: Varad Gautam <varad.gautam@collabora.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de> (v4)
Cc: Lucas Stach <l.stach@pengutronix.de>
2017-06-09 14:12:37 +01:00
Varad Gautam
e0965a2c8e gallium: introduce format modifier querying
format modifiers tokens are driver specific, and hence, need to come
in from the driver. this allows drivers to be queried for supported
format modifiers for EGL_EXT_image_dma_buf_import_modifiers.

v2: rebase to master.
v3: drivers must return false on query failure.
v4: use pscreen->is_format_supported instead of adding a separate
    format query handle, remove PIPE_CAP_QUERY_DMABUF_ATTRIBS.
    (Lucas Stach)
v5: add external_only parameter.

Signed-off-by: Varad Gautam <varad.gautam@collabora.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2017-06-09 14:12:37 +01:00