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i965/cnl: Implement depth count workaround

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Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Ben Widawsky 2016-01-04 10:48:39 -08:00 • committed by Anuj Phogat
parent 8c43e33560
commit 640f5d3957
1 changed files with 8 additions and 0 deletions
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8
src/mesa/drivers/dri/i965/brw_queryobj.c
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@ -111,6 +111,14 @@ brw_write_depth_count(struct brw_context *brw, struct brw_bo *query_bo, int idx)
if (brw->gen == 9 && brw->gt == 4)
flags |= PIPE_CONTROL_CS_STALL;
if (brw->gen >= 10) {
/* "Driver must program PIPE_CONTROL with only Depth Stall Enable bit set
* prior to programming a PIPE_CONTROL with Write PS Depth Count Post sync
* operation."
*/
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
}
brw_emit_pipe_control_write(brw, flags,
query_bo, idx * sizeof(uint64_t),
0, 0);