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i965/cnl: Start using CNL MOCS defines

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CNL MOCS defines are duplicates of SKL MOCS defines.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Anuj Phogat 2017-05-15 13:04:57 -07:00
parent 111881abac
commit 8c43e33560
4 changed files with 16 additions and 4 deletions
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6
src/mesa/drivers/dri/i965/brw_blorp.c
View file

@ -110,9 +110,9 @@ brw_blorp_init(struct brw_context *brw)
brw->blorp.exec = gen9_blorp_exec;
break;
case 10:
brw->blorp.mocs.tex = SKL_MOCS_WB;
brw->blorp.mocs.rb = SKL_MOCS_PTE;
brw->blorp.mocs.vb = SKL_MOCS_WB;
brw->blorp.mocs.tex = CNL_MOCS_WB;
brw->blorp.mocs.rb = CNL_MOCS_PTE;
brw->blorp.mocs.vb = CNL_MOCS_WB;
brw->blorp.exec = gen10_blorp_exec;
break;
default:

8
src/mesa/drivers/dri/i965/brw_state.h
View file

@ -407,6 +407,14 @@ void upload_gs_state_for_tf(struct brw_context *brw);
/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
#define SKL_MOCS_PTE (1 << 1)
/* Cannonlake: MOCS is now an index into an array of 62 different caching
* configurations programmed by the kernel.
*/
/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
#define CNL_MOCS_WB (2 << 1)
/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
#define CNL_MOCS_PTE (1 << 1)
#ifdef __cplusplus
}
#endif

2
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View file

@ -64,12 +64,14 @@ uint32_t tex_mocs[] = {
[7] = GEN7_MOCS_L3,
[8] = BDW_MOCS_WB,
[9] = SKL_MOCS_WB,
[10] = CNL_MOCS_WB,
};
uint32_t rb_mocs[] = {
[7] = GEN7_MOCS_L3,
[8] = BDW_MOCS_PTE,
[9] = SKL_MOCS_PTE,
[10] = CNL_MOCS_PTE,
};
static void

4
src/mesa/drivers/dri/i965/genX_state_upload.c
View file

@ -344,7 +344,9 @@ genX(emit_vertex_buffer_state)(struct brw_context *brw,
#endif
#endif
#if GEN_GEN == 9
#if GEN_GEN == 10
.VertexBufferMOCS = CNL_MOCS_WB,
#elif GEN_GEN == 9
.VertexBufferMOCS = SKL_MOCS_WB,
#elif GEN_GEN == 8
.VertexBufferMOCS = BDW_MOCS_WB,