Commit graph

172753 commits

Author SHA1 Message Date
Alyssa Rosenzweig
c696fc4392 glsl: Assume use_scoped_barrier
True for all backends supporting barriers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23191>
2023-06-13 16:36:10 +00:00
Alyssa Rosenzweig
d8a45db591 ac/llvm: Drop memory_barrier_buffer impl
Both radeonsi and radv use scoped barriers, so this should not be possible to
hit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23191>
2023-06-13 16:36:10 +00:00
Alyssa Rosenzweig
749b4817ad ntt: Use scoped barriers
In addition to bringing us one backend closer to the scoped-only future, this
improves the generated code in cases like:

   memoryBarrierBuffer();
   memoryBarrierShared();
   controlBarrier();

With scoped_barriers + nir_opt_combine_barriers, we now emit only one MEMBAR
instruction (and a BARRIER) rather than two MEMBARs.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23191>
2023-06-13 16:36:10 +00:00
Alyssa Rosenzweig
d3aca1a758 ttn: Emit scoped barriers when needed
As we start converting more backends over.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23191>
2023-06-13 16:36:10 +00:00
Alyssa Rosenzweig
4368365fcf ir3: Drop reference to unsupported intrinsic
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23191>
2023-06-13 16:36:10 +00:00
Alyssa Rosenzweig
09b5e2a786 vtn: Handle atomic counter semantics
This can happen for GLSL-environment SPIR-V.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Suggested-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23191>
2023-06-13 16:36:10 +00:00
Erico Nunes
98fde58b3a ci: temporarily disable lima farm
The lab is currently experiencing network instability with the ISP.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23623>
2023-06-13 16:07:55 +00:00
Thomas H.P. Andersen
20e6c31ba6 r600: tgsi cleanup
337dc7d766 removed the usage of these
fields in struct r600_shader_ctx

Cleaning this up will let us drop tgsi_array_info in a later MR

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23535>
2023-06-13 15:51:54 +00:00
Karol Herbst
50085ccd11 docs: improve OpenCL features
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed by Nora Allen <blackcatgames@protonmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23622>
2023-06-13 15:47:02 +00:00
Timur Kristóf
d3d55f7747 radv: Leave primitive reset index at max on GFX8+.
GFX8+ only compares the bits according to the index type by default
(GFX9 can be changed by VGT_MULTI_PRIM_IB_RESET_EN.MATCH_ALL_BITS),
so we can always leave the programmed value at the maximum.

This reduces context rolls on GFX8+ when primitive restart is used.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23459>
2023-06-13 15:26:47 +00:00
Timur Kristóf
ce3b84cc62 radv: Remove primitive reset index from late scissor workaround.
Primitive reset has a corresponding dirty state which is already
included the used_states so it is not necessary to also check
the primitive reset index here.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23459>
2023-06-13 15:26:47 +00:00
Christian Gmeiner
3d49619071 etnaviv: add support for performance warnings
These performance warnings should help to get a better understanding
where we doing non performance optimal things.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23615>
2023-06-13 14:48:05 +00:00
Tapani Pälli
00a91d8870 anv: use workaround framework for 1408224581, 14014097488
This makes sure we apply WA only when it is required, these issues
do not happen for later MTL steppings.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23596>
2023-06-13 13:27:30 +00:00
Tapani Pälli
c7c902cdbf iris: use workaround framework for 1408224581, 14014097488
This makes sure we apply WA only when it is required, these issues
do not happen for later MTL steppings.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23596>
2023-06-13 13:27:30 +00:00
Tapani Pälli
15433897b2 intel/dev: add parentheses around intel_needs_workaround macro
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23596>
2023-06-13 13:27:30 +00:00
Pavel Ondračka
4c28c5b074 r300: be more agressive when merging A0 loads
Specifically we would bail out previously when encountering any
control flow, now we would optimize it even when the second ARL/ARR
is inside a lower level if/else branch.

shader-db

RV530:
total instructions in shared programs: 132020 -> 131924 (-0.07%)
instructions in affected programs: 3374 -> 3278 (-2.85%)
helped: 4
HURT: 0

RV370:
no change (no control flow there)

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23560>
2023-06-13 11:52:48 +00:00
Pavel Ondračka
6de9152e3a r300: remove duplicate ARRs
We already do this for ARL, so just generalize the pass.

shader-db

RV530:
total instructions in shared programs: 132235 -> 132020 (-0.16%)
instructions in affected programs: 8492 -> 8277 (-2.53%)
helped: 41
HURT: 1
total temps in shared programs: 16900 -> 16887 (-0.08%)
temps in affected programs: 83 -> 70 (-15.66%)
helped: 13
HURT: 0

RV370:
total instructions in shared programs: 82395 -> 82320 (-0.09%)
instructions in affected programs: 4715 -> 4640 (-1.59%)
helped: 33
HURT: 1
total temps in shared programs: 12316 -> 12305 (-0.09%)
temps in affected programs: 75 -> 64 (-14.67%)
helped: 11
HURT: 0

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23560>
2023-06-13 11:52:48 +00:00
Pavel Ondračka
a1a981f6c1 r300: optimize the load A0 pattern from wined3d
Shader-db

RV530:
total instructions in shared programs: 129701 -> 128733 (-0.75%)
instructions in affected programs: 7011 -> 6043 (-13.81%)
helped: 48
HURT: 0
total loops in shared programs: 15 -> 11 (-26.67%)
loops in affected programs: 4 -> 0
helped: 4
HURT: 0
total temps in shared programs: 16819 -> 16832 (0.08%)
temps in affected programs: 70 -> 83 (18.57%)
helped: 0
HURT: 13
total consts in shared programs: 90830 -> 90813 (-0.02%)
consts in affected programs: 4335 -> 4318 (-0.39%)
helped: 17
HURT: 0

RV370:
total instructions in shared programs: 82027 -> 81215 (-0.99%)
instructions in affected programs: 5456 -> 4644 (-14.88%)
helped: 39
HURT: 0
total temps in shared programs: 12262 -> 12273 (0.09%)
temps in affected programs: 64 -> 75 (17.19%)
helped: 0
HURT: 11
total consts in shared programs: 79119 -> 79104 (-0.02%)
consts in affected programs: 3825 -> 3810 (-0.39%)
helped: 15
HURT: 0
GAINED:5

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9157
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23560>
2023-06-13 11:52:48 +00:00
Pavel Ondračka
886a6aa5be r300: move the ROUND+ARL->ARR fusing to main optimization loop
Its particularly important to have the copy-propagate pass run first.
So that when the round is vectorized, we don't have to follow the MOVs
to find out if it leads to ARL or not (we don't vectorize ARR/ARL at the
moment).

No shader-db change.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23560>
2023-06-13 11:52:48 +00:00
Pavel Ondračka
f82574fb2c r300: move the ARL merging pass up in the opt loop
Specifically after the first copy propagate run but before the
second one. Removal of ARLs will enable the copy propagate to be more
aggresive, as it is very carefull in such cases.

shader-db

RV530:
total instructions in shared programs: 131861 -> 131503 (-0.27%)
instructions in affected programs: 23949 -> 23591 (-1.49%)
helped: 199
HURT: 15
total temps in shared programs: 16997 -> 16903 (-0.55%)
temps in affected programs: 767 -> 673 (-12.26%)
helped: 69
HURT: 9

RV370:
total instructions in shared programs: 82360 -> 82027 (-0.40%)
instructions in affected programs: 19516 -> 19183 (-1.71%)
helped: 183
HURT: 15
total temps in shared programs: 12370 -> 12262 (-0.87%)
temps in affected programs: 664 -> 556 (-16.27%)
helped: 73
HURT: 0

The hurt programs are due to some constant load being copy propagated
which leads to bad interaction with source conflict resolve pass later.

v2: add missing shader type initialized to the tests. Previously we were
checking for has_omod which also practically means we have a fragment
shader, however its less readable.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23560>
2023-06-13 11:52:48 +00:00
Pavel Ondračka
453201fe74 r300: move nir stuff to r300_nir file
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23560>
2023-06-13 11:52:48 +00:00
Martin Roukala (né Peres)
6d60e38dd7 zink/ci: enable zink-radv-vangogh-valve for pre-merge testing
This should allow us to catch regressions without me having to bisect
them after they land :p

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8396
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21730>
2023-06-13 11:17:04 +00:00
Martin Roukala (né Peres)
741bfb52e6 zink/ci: add more tests to the flake list of vangogh
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21730>
2023-06-13 11:17:04 +00:00
Martin Roukala (né Peres)
e01f7323de ci/b2c: change the default first-console-activity timeout to 2 minutes
Having a high value for the first activity timeout made sense back in
the days when the machine may not be associated with salad early... but
this isn't the case anymore!

So let's go with a very conservative value of 2 minutes to boot :)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21730>
2023-06-13 11:17:04 +00:00
Juan A. Suarez Romero
acf6364068 broadcom/ci: update expected results
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23617>
2023-06-13 10:55:16 +00:00
Corentin Noël
3f71ed9e7e gallium: Rename dri_init_screen_helper into dri_init_screen
Makes it more obvious that this function is actually initializing the dri_screen
and not some helper.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23054>
2023-06-13 10:10:42 +00:00
Corentin Noël
ad0bcd75fd gallium: Use the common destroy function on screen initialization failure
Avoid leaking configuration options on initialization failure.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23054>
2023-06-13 10:10:41 +00:00
Corentin Noël
4d25ae350f gallium: Only call dri_init_options when the screen is actually created
Avoid calling this function on screen creation failure as we will discard its
result right after.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23054>
2023-06-13 10:10:41 +00:00
Corentin Noël
09f65f266e pipe-loader: Do not destroy the winsys on screen creation failure
The winsys is always destroyed on pipe_loader_device release.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9020
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23054>
2023-06-13 10:10:41 +00:00
Corentin Noël
6b4f80f7f0 pipe-loader: Document the behavior regarding screen creating failures
Avoid inconsistent behavior on screen creation failures which might lead
to double free issues.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23054>
2023-06-13 10:10:41 +00:00
Corentin Noël
744c849a08 gallium: Rename dri_destroy_screen_helper into dri_release_screen
This function is actually used before the use of dri_init_screen_helper so
it is not exactly releasing the memory allocated by the screen helper.

Also clear the base.screen variable after destroy to make this function
reentrant.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23054>
2023-06-13 10:10:41 +00:00
Corentin Noël
c2d90602ca gallium: Incorporate the device release in dri_destroy_screen_helper
The code to release the device was actually always used after the call
to this function.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23054>
2023-06-13 10:10:41 +00:00
Samuel Pitoiset
5b96a6cc2f radv/ci: update the list of expected failures on STONEY
Spurious changes but the failures are weird anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23209>
2023-06-13 07:52:44 +02:00
Samuel Pitoiset
25d46958c5 radv: disable HTILE compression only when layouts are compressed
On RDNA2, VRS rates are part of the HTILE buffer but if we disable
HTILE completely for eg. GENERAL, VRS rates aren't read by the hw.

Fix this by disabling HTILE compression which should have the same
effect without VRS.

Fixes recent
dEQP-VK.fragment_shading_rate.renderpass2.monolithic.attachment_rate.misc.*

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23209>
2023-06-13 07:52:44 +02:00
Samuel Pitoiset
9b141e2565 radv: emit DB_RENDER_CONTROL as part of the framebuffer
DB_RENDER_CONTROL controls whether depth/stencil rendering should be
compressed. Emitting this register as part of the framebuffer will
allow us to keep HTILE enabled for VRS rates, instead of disabling it
completely.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23209>
2023-06-13 07:52:43 +02:00
Samuel Pitoiset
b9237bdc6b radv: reset more DB registers when emitting a null ds target
PAL does that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23209>
2023-06-13 07:52:43 +02:00
Samuel Pitoiset
42dbfad01d radv: add a helper for emitting a null depth/stencil target
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23209>
2023-06-13 07:52:43 +02:00
Qiang Yu
b4403d8985 radeonsi: enable aco support for compute shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23540>
2023-06-13 03:41:03 +00:00
Qiang Yu
df4f84f806 radeonsi: fix crash when AMD_DEBUG=cs,initnir
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23540>
2023-06-13 03:41:02 +00:00
Qiang Yu
5f52f8a6ba ac/llvm,radeonsi: lower nir_load_user_data_amd in abi
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23540>
2023-06-13 03:41:02 +00:00
Qiang Yu
0a7014328f radeonsi: add scratch_offset arg for aco cs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23540>
2023-06-13 03:41:02 +00:00
Timothy Arceri
a337a0c807 st/glsl: move linking code to the same st file
Since they call one another this makes it easier to see what is
going on without looking in multiple files.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23541>
2023-06-13 02:25:54 +00:00
Jesse Natalie
92dcaf7deb dxil: Remove custom SSBO lowering
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23173>
2023-06-13 00:43:37 +00:00
Jesse Natalie
16aeaad73e microsoft/compiler: Don't over-align raw buffer load/store intrinsics
DXC doesn't generate these for raw loads/stores, only structured, and
old WARP had bugs with this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23173>
2023-06-13 00:43:37 +00:00
Jesse Natalie
38617dc726 microsoft/compiler: Don't lower bit sizes for movs
Otherwise we run into problems by putting this optimization loop
before I/O lowering, where there might still be 8-bit values that
haven't been lowered to 16 or 32. Once that's done, any remaining
movs or vec ops will have higher bit sizes already.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23173>
2023-06-13 00:43:36 +00:00
Jesse Natalie
ecfbc16f61 dxil: Delete load_ubo_dxil intrinsic
Instead of splitting unaligned UBO loads while still using derefs,
and then lowering load_ubo to load_ubo_dxil in lower_loads_stores_to_dxil,
use lower_mem_access_bit_sizes and lower_ubo_vec4 to handle load size and
alignment restrictions while converting to load_ubo_vec4 instead, which
has the same semantics as load_ubo_dxil.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3842
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23173>
2023-06-13 00:43:36 +00:00
Jesse Natalie
42877c8b63 dxil: Don't generate load_ubo_dxil directly
Just use load_ubo and let it get lowered appropriately later on.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23173>
2023-06-13 00:43:36 +00:00
Jesse Natalie
6a5ed9e2e9 microsoft/compiler: Support load_ubo_vec4
Add support for 16-bit UBO loads, delete handling of byte-addressed
UBO loads (which I think was never used anyway) and add handling
for the component const index to optimize out unneeded extractResults.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23173>
2023-06-13 00:43:36 +00:00
Jesse Natalie
f960b37986 spirv2dxil: Don't lower shared/temp to explicit I/O
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23173>
2023-06-13 00:43:36 +00:00
Jesse Natalie
f121d8fe12 microsoft/compiler: Un-lower shared/scratch to derefs
Derefs have index-based access semantics, which means we don't need
custom intrinsics to encode an index instead of a byte offset.

Remove the "masked" store intrinsics and just emit the pair of atomics
directly. This massively reduces duplication between scratch, shared,
and constant, while also moving more things into nir so more optimizations
can be done.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23173>
2023-06-13 00:43:36 +00:00