fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-06 02:58:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: emit DB_RENDER_CONTROL as part of the framebuffer

Browse source 
DB_RENDER_CONTROL controls whether depth/stencil rendering should be
compressed. Emitting this register as part of the framebuffer will
allow us to keep HTILE enabled for VRS rates, instead of disabling it
completely.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23209>
This commit is contained in:
Samuel Pitoiset 2023-05-24 15:56:08 +02:00
parent b9237bdc6b
commit 9b141e2565
3 changed files with 10 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1904,7 +1904,6 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
if (cmd_buffer->state.emitted_graphics_pipeline->ms.min_sample_shading != pipeline->ms.min_sample_shading ||
cmd_buffer->state.emitted_graphics_pipeline->uses_out_of_order_rast != pipeline->uses_out_of_order_rast ||
cmd_buffer->state.emitted_graphics_pipeline->uses_vrs_attachment != pipeline->uses_vrs_attachment ||
cmd_buffer->state.emitted_graphics_pipeline->db_render_control != pipeline->db_render_control ||
cmd_buffer->state.emitted_graphics_pipeline->rast_prim != pipeline->rast_prim)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
@ -1918,6 +1917,9 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
if (cmd_buffer->state.emitted_graphics_pipeline->db_shader_control !=
pipeline->db_shader_control)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE;
if (cmd_buffer->state.emitted_graphics_pipeline->db_render_control != pipeline->db_render_control)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
}
radeon_emit_array(cmd_buffer->cs, pipeline->base.cs.buf, pipeline->base.cs.cdw);
@ -2661,10 +2663,8 @@ radv_emit_rasterization_samples(struct radv_cmd_buffer *cmd_buffer)
const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer);
unsigned ps_iter_samples = radv_get_ps_iter_samples(cmd_buffer);
const struct radv_rendering_state *render = &cmd_buffer->state.render;
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
unsigned db_render_control = cmd_buffer->state.db_render_control;
unsigned pa_sc_mode_cntl_1;
pa_sc_mode_cntl_1 =
@ -2700,11 +2700,6 @@ radv_emit_rasterization_samples(struct radv_cmd_buffer *cmd_buffer)
pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(1);
}
if (pdevice->rad_info.gfx_level >= GFX11) {
radv_gfx11_set_db_render_control(cmd_buffer->device, render->max_samples, &db_render_control);
}
radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, db_render_control);
radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, pa_sc_mode_cntl_1);
}
@ -2895,6 +2890,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_
uint32_t db_z_info = ds->db_z_info;
uint32_t db_stencil_info = ds->db_stencil_info;
uint32_t db_htile_surface = ds->db_htile_surface;
uint32_t db_render_control = ds->db_render_control | cmd_buffer->state.db_render_control;
if (!radv_layout_is_htile_compressed(
cmd_buffer->device, image, layout,
@ -2909,6 +2905,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_
db_htile_surface &= C_028ABC_VRS_HTILE_ENCODING;
}
radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, db_render_control);
radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);

4
src/amd/vulkan/radv_device.c
View file

@ -1883,6 +1883,10 @@ radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buff
ds->db_htile_surface |= S_028ABC_VRS_HTILE_ENCODING(V_028ABC_VRS_HTILE_4BIT_ENCODING);
}
}
if (device->physical_device->rad_info.gfx_level >= GFX11) {
radv_gfx11_set_db_render_control(device, iview->image->vk.samples, &ds->db_render_control);
}
} else {
const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];

1
src/amd/vulkan/radv_private.h
View file

@ -1512,6 +1512,7 @@ struct radv_ds_buffer_info {
uint32_t db_z_info2; /* GFX9 only */
uint32_t db_stencil_info2; /* GFX9 only */
uint32_t db_render_override2;
uint32_t db_render_control;
};
void radv_initialise_color_surface(struct radv_device *device, struct radv_color_buffer_info *cb,