This switches to disk_cache instead of our own mechanism which only
stored meta shaders when the logical was destroyed.
Meta shaders are still stored separately from the application shaders
because they are common to all applications on a given GPU/Mesa version.
The default cache is 32MiB which should be large enough.
This fixes massive stuttering in FF7 Rebirth but all apps are
technically affected.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33370>
Instead of using the default one provided by the physical device.
This will be used by RADV to store meta shaders to a separate single
cache file.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33370>
The fix in e7ac1094f6 to emit preamble defs in the correct block would
move the cursor of the builder that is later used to insert descriptor
prefetches, emitting them at the wrong place. Fix this by resetting the
cursor before emitting the prefetches.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: e7ac1094f6 ("ir3: rematerialize preamble defs in block dominated by sources")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33399>
Add updated Alder Lake P firmware directly to the rootfs, as it is newer
than the version available in the Debian package. This is required for
the Xe kernel driver and is recommended for i915.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
Intel switched to exclusively using per-tile sysfs interfaces in Xe.
The locations and names of the sysfs attributes also changed compared
to i915, so update the intel-gpu-freq.sh script to work with both KMDs.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
We rely on the panfrost_model details around the codebase, if it's not
known this is a problem.
As a result, we will now disallow anything that isn't known like what
we do on Gallium.
Fixes: c95ef9e323 ("panvk: Fix NULL deref on model name when device isn't supported")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Suggested-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
Was named source 2, but it's actually source 0.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
THe enum variant for u64 was actually 32-bit making all 64-bit operation
wrong.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: 7d0dc3d30c ("pan/decode: Add a helper to print CS binaries without interpreting them")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
TEX_FETCH doesn't have the CUBE dimension, this was working on v9 and
v10 but this fails on Avalon.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: ce52b6d359 ("pan/bi: Rework indices for tex on Valhall")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
This was removed on v11, we currently don't use it so to ensure no one
start using it, let's just mark it as reserved.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
This src1 expect lanes, isn't widen and have a size of 8-bit (5-bit on
Valhall, 4-bit on Avalon)
We also now disallow swizzle lowering on it. (even on Bifrost)
Fixes: 316486dd9f ("pan/va: Add initial ISA.xml for Valhall")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
We were wrongly defining values that select more than one byte.
The swizzle used for H01 was working fine for v9 and v10, but this
generate an invalid encoding on Avalon.
This fixes this by using B00 variant as we are only using 8-bit sources.
Fixes: f45654af59 ("pan/va: Add packing routines")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
We were hardcoding table 61 and index 0 for IDVS based usage and this
could have been misused.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: f45654af59 ("pan/va: Add packing routines")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
The offset of dest should be 40, not 48.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: 486c341769 ("panfrost: Add architecture description XML for v10")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
Those were supposed to use BITFIELD_BIT.
Fixes: 2237cff1af ("panfrost: Report default value for GROUP_PRIORITIES_INFO in drm-shim")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
Somewhere between writing c1510ad72e ("nak: Optimize bindless to cbuf
textures on Volta+") and me rebasing it a year later, we switched to
using the NV-specific ldc_nv intrinsic for cbuf loads. It's basically
the same as load_ubo but we're detecting the wrong intrinsic so the
optimization does nothing.
Fixes: c1510ad72e ("nak: Optimize bindless to cbuf textures on Volta+")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33398>
These have been switching between failing and passing recently. Not
really sure what's going on here, but we don't want the CI to flip
randomly between failing and passing, so let's mark them as flakes.
Backport-to: 25.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33381>
I think this was broken as there might be a store_output with
less than 4 components to a location that shouldn't be smoothed
anyway (i.e. not the first one).
nir_lower_poly_line_smooth now handles the case where the first location
doesn't have 4 components.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33340>
RADV needs this to skip if there is no alpha component
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33340>
The VK spec says:
coverage value is multiplied into the color location 0’s
alpha value after fragment shading
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33340>
The if is really short so it should really use a conditional select,
but this pass is called too late go through all the usual lowerings
and opts.
Foz-DB Navi21:
Totals from 1128 (1.42% of 79377) affected shaders:
MaxWaves: 29358 -> 29342 (-0.05%)
Instrs: 552306 -> 549668 (-0.48%); split: -0.58%, +0.10%
CodeSize: 2796392 -> 2782360 (-0.50%); split: -0.59%, +0.08%
Latency: 2574361 -> 2566482 (-0.31%); split: -0.47%, +0.16%
InvThroughput: 644047 -> 647500 (+0.54%); split: -0.18%, +0.72%
Copies: 37521 -> 36460 (-2.83%); split: -2.92%, +0.09%
Branches: 12009 -> 10157 (-15.42%)
VALU: 350886 -> 349199 (-0.48%); split: -0.64%, +0.16%
SALU: 104459 -> 105415 (+0.92%); split: -0.00%, +0.92%
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33340>
This should have been included in the commits that introduced the
extensions.
Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Fixes: 00fb0f5ec2 ("panvk: enable KHR_separate_depth_stencil_layouts")
Fixes: 935cadbc2e ("panvk: enable VK_KHR_depth_stencil_resolve")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33394>
The zink-venus-lvp-full job was intended to be a nightly job, but it
was missing the proper manual rules for that.
Fixes: 7bf4d6a4db ("zink/ci: Add a fraction for zink-venus-lvp")
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Martin Roukala <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33393>
This will be useful for pulling constants in device bound shaders. A64
allows us to put the constants anywhere.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32895>
Now using the same model as the compute shader.
As a result we temporarily disable the use of the Inline register for
providing push constants on Task & Mesh shaders. Since that register
is also available on the compute shader we'll try to find a way to use
the same mechanism for all 3 shaders in another MR and bring back that
optimization.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32895>
