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pan/bi: Fix invalid CLPER encoding

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This src1 expect lanes, isn't widen and have a size of 8-bit (5-bit on
Valhall, 4-bit on Avalon)

We also now disallow swizzle lowering on it. (even on Bifrost)

Fixes: 316486dd9f ("pan/va: Add initial ISA.xml for Valhall")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
This commit is contained in:
Mary Guillemard 2025-01-30 11:56:25 +00:00 • committed by Marge Bot
parent 637cb0a993
commit b00c09b920
4 changed files with 11 additions and 6 deletions
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5
src/panfrost/compiler/bi_lower_swizzle.c
View file

@ -54,12 +54,17 @@ lower_swizzle(bi_context *ctx, bi_instr *ins, unsigned src)
case BI_OPCODE_CSEL_V2I16:
case BI_OPCODE_CSEL_V2S16:
case BI_OPCODE_CSEL_V2U16:
break;
/* Despite ostensibly being 32-bit instructions, CLPER does not
* inherently interpret the data, so it can be used for v2f16
* derivatives, which might require swizzle lowering */
case BI_OPCODE_CLPER_I32:
case BI_OPCODE_CLPER_OLD_I32:
if (src == 0)
break;
else
return;
/* Similarly, CSEL.i32 consumes a boolean as a 32-bit argument. If the
* boolean is implemented as a 16-bit integer, the swizzle is needed

8
src/panfrost/compiler/bifrost_compile.c
View file

@ -1779,7 +1779,7 @@ bi_emit_derivative(bi_builder *b, bi_index dst, nir_intrinsic_instr *instr,
*/
if (nir_def_all_uses_ignore_sign_bit(&instr->def) && !coarse) {
left = s0;
right = bi_clper(b, s0, bi_imm_u32(axis), BI_LANE_OP_XOR);
right = bi_clper(b, s0, bi_imm_u8(axis), BI_LANE_OP_XOR);
} else {
bi_index lane1, lane2;
if (coarse) {
@ -1792,8 +1792,8 @@ bi_emit_derivative(bi_builder *b, bi_index dst, nir_intrinsic_instr *instr,
lane2 = bi_iadd_u32(b, lane1, bi_imm_u32(axis), false);
}
left = bi_clper(b, s0, lane1, BI_LANE_OP_NONE);
right = bi_clper(b, s0, lane2, BI_LANE_OP_NONE);
left = bi_clper(b, s0, bi_byte(lane1, 0), BI_LANE_OP_NONE);
right = bi_clper(b, s0, bi_byte(lane2, 0), BI_LANE_OP_NONE);
}
bi_fadd_to(b, sz, dst, right, bi_neg(left));
@ -2086,7 +2086,7 @@ bi_emit_intrinsic(bi_builder *b, nir_intrinsic_instr *instr)
bi_subgroup_from_cluster_size(pan_subgroup_size(b->shader->arch));
bi_clper_i32_to(b, dst,
bi_src_index(&instr->src[0]),
bi_src_index(&instr->src[1]),
bi_byte(bi_src_index(&instr->src[1]), 0),
inactive_result, lane_op, subgroup);
break;
}

2
src/panfrost/compiler/valhall/ISA.xml
View file

@ -1977,7 +1977,7 @@
derivatives in fragment shaders.
</desc>
<src>A</src>
<src widen="true">B</src>
<src lanes="true" size="8">B</src>
<subgroup/>
<lane_op/>
<inactive_result/>

2
src/panfrost/compiler/valhall/test/assembler-cases.txt
View file

@ -32,7 +32,7 @@ e6 00 00 00 00 c1 91 06 MOV.i32 r1, core_id.w0
00 00 00 00 00 c0 00 78 NOP.end
40 c4 c0 9c 01 c1 f0 00 ICMP_OR.u32.gt.m1 r1, ^r0, 0x1000000.b3, 0x0
42 00 00 18 02 40 61 50 STORE.i32.slot0.reconverge @r0, ^r2, offset:0
00 c9 8f 12 30 c0 a0 00 CLPER.i32.f1 r0, r0, 0x7060504.b0
00 c9 8f 12 30 c0 a0 00 CLPER.i32.f1 r0, r0, 0x7060504.b00
00 00 00 30 00 c7 90 00 S8_TO_S32 r7, r0.b3
00 00 00 20 00 c6 90 00 S8_TO_S32 r6, r0.b2
00 00 00 00 00 c4 90 00 S8_TO_S32 r4, r0.b0