Commit graph

66052 commits

Author SHA1 Message Date
Chris Forbes
c442745981 i965: Have mesa flag BRW_NEW_TEXTURE_BUFFER when a TexBO binding changes
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-10-16 22:31:43 +13:00
Chris Forbes
be5df28941 i965: Add new dirty flag for new TexBOs.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-10-16 22:31:43 +13:00
Chris Forbes
8db38ba4d2 mesa: Mark buffer objects that are used as TexBOs
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-10-16 22:31:43 +13:00
Chris Forbes
fe3133fe78 mesa: Mark buffer objects which are bound as UBOs
When a buffer object is bound to one of the indexed uniform buffer
binding points, assume that from that point on it may be used as
a uniform buffer.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-10-16 22:31:43 +13:00
Chris Forbes
3d989467f1 mesa: Add usage history bitfield to buffer objects
In the drivers, we occasionally want to reallocate the backing
store for a buffer object; often to avoid waiting for the GPU
to be finished with the previous contents.

At the point that happens, we don't have a good way of determining
where else the buffer object may be bound, and so no good way of
determining which dirty flags need to be raised -- it's fairly
expensive to go looking at all the possible binding points.

Until now, we've considered any BO to be possibly bound as a UBO or
TexBO, and flagged all that state to be reemitted.

Instead, remember what kinds of binding point this buffer has ever
been used with, so that the drivers can flag only what they need.
I don't expect these bits to ever be reset, but that doesn't matter
for reasonable apps.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-10-16 22:31:43 +13:00
Emil Velikov
79d09a4b12 vc4: correctly include the source files
The kernel files are built into a separate static library and
all the functions that require it are already wrapped in ifdef
USE_VC4_SIMULATOR. Don't forget the header file :)

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-10-16 10:00:14 +01:00
Connor Abbott
70fa53be5e i965/fs: don't make a fake ir_texture in the Mesa IR frontend
Now that we've made all the texture emit code mostly independent of GLSL
IR, this isn't necessary any more.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:05:25 -07:00
Kenneth Graunke
b17f571945 i965/fs: Refactor the texture emission logic into a single function.
Before, we had 3 different emit functions for various different gen's,
as well as some ancilliary work that was the same across all gen's which
was either contained in functions or duplicated across the GLSL IR and
Mesa IR backends. Now, we have a single method, emit_texture(), that
takes all the information needed to make a texture instruction and
handles all the setup, and all we have to do to emit a texture
instruction while converting from GLSL IR, Mesa IR, or any new backend
is to extract the information emit_texture() needs and then call it.

v2: Significant rebasing (by Ken).

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:05:22 -07:00
Connor Abbott
9e95d8ebf8 i965/fs: Make gather_channel() not use ir_texture.
Our new IR won't have ir_texture objects.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:05:20 -07:00
Connor Abbott
12d9a8cd86 i965/fs: Make swizzle_result() not use ir_texture.
Our new IR won't have ir_texture objects.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:05:19 -07:00
Connor Abbott
cf94dfdb96 i965/fs: fix integer textures with swizzles
This happened to work before, but it would convert the output to a float
and then back to an integer which seems bad.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:05:16 -07:00
Connor Abbott
7c8f0b7cd9 i965/fs: don't pass in ir_texture to emit_texture_*
At this point, the only thing it's used for is the opcode.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:05:14 -07:00
Connor Abbott
4bffcb7e8e i965/fs: don't use ir->type in emit_texture_gen4()
We already have the type from the original destination.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:05:05 -07:00
Connor Abbott
eaadc43192 i965/fs: Don't use ir->lod_info.grad.dPd<x,y> in emit_texture_*.
This drops a dependency on ir_texture objects.

v2 (Ken): Rename lod_components to grad_components, as it only has a
          meaningful value for ir_txd.  We could set it to 1 for TXL,
          but there's no real need.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:05:00 -07:00
Connor Abbott
cbde5407c9 i965/fs: Don't use ir->coordinate in emit_texture_*.
This drops a dependency on ir_texture objects.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:04:58 -07:00
Connor Abbott
a8905e8c09 i965/fs: make rescale_texcoord() not use ir_texture.
Our new IR won't have ir_texture objects, but using glsl_type is fine.

v2 (Ken): Drop redundant ir->coordinate NULL check; rebase.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:04:56 -07:00
Connor Abbott
e599837fed i965/fs: Make emit_mcs_fetch() not use ir_texture.
Our new IR won't have ir_texture objects.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:04:54 -07:00
Kenneth Graunke
465373535e i965/fs: Rename "length" to "components" in emit_mcs_fetch().
This is slightly clearer.  Based on a patch by Connor Abbott.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:04:52 -07:00
Connor Abbott
fa212c6b98 i965: Make brw_texture_offset() not use ir_texture.
Our new IR won't have ir_texture objects.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:04:50 -07:00
Connor Abbott
a71455bc99 i965/fs: don't use ir->offset in emit_texture_gen5.
v2 (Ken): Refactor the Gen7 code separately; rebase.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:04:47 -07:00
Kenneth Graunke
1f76fcf231 i965/fs: Move texel offset handling to visit(ir_texture *).
This moves the handling of non-constant texel offset subexpression trees
to the place where we visit other such subtrees.  It also removes some
uses of ir->offset in emit_texture_gen7, which will be useful when we
write the backend for our new upcoming IR.

Based on a patch by Connor Abbott.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:04:45 -07:00
Kenneth Graunke
cee2027574 i965: Drop ir->op != ir_txf condition in offset checking.
brw_lower_unnormalized_offset sets ir->offset to NULL if it applies the
texelFetchOffset workarounds, so there's no need to special case it
here---there won't be an offset for ir_txf.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:04:43 -07:00
Kenneth Graunke
a2c3cfbb4d i965: Restore a lost comment about TXF offset bugs.
Eric's original code to work around TXF offset bugs contained a comment
explaining the problem, which was lost when Chris generalized it to an
IR transformation (in commit 598ca510b8).

This commit adds the original comment to the newer code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-10-15 17:04:27 -07:00
Rob Clark
652b8fbbbb freedreno/ir3: large const support
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:49 -04:00
Rob Clark
e71a3f80fb freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Rob Clark
dd332fe641 freedreno: fix layer_stride
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Rob Clark
8233b36a17 freedreno: inline fd_draw_emit()
Manual LTO

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Rob Clark
368466b7b7 freedreno/ir3: optimize shader key comparision
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Rob Clark
d595987ea3 freedreno/a3xx: refactor/optimize emit
Because we reuse various bits of emit code (for state/vertex/prog/etc)
for both regular draws and internal draws (gmem<->mem, clear, etc), the
number of parameters getting passed around has been growing.  Refactor
to group these into fd3_emit.  This simplifies fxn signatures, avoids
passing around shader key on the stack, etc.  It also gives us a nice
place to cache shader-variant lookup to avoid looking up shader variants
multiple times per draw (without having to *also* pass them around as
fxn args everywhere).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Rob Clark
d5d80b3739 freedreno/a3xx: refactor vertex state emit
Get rid of fd3_vertex_buf and use fd_vertex_state directly for all
draws.  Removes a tiny bit of CPU overhead for munging around the vertex
state every time it is emitted, but more importantly it cleans things up
for later optimizations, so the emit paths don't have to special case
internal draws (gmem<->mem, clears, etc) with regular draws.

Instead of constructing fd3_vertex_buf array each time for internal
draws, and context init time pre-create solid_vbuf_state and
blit_vbuf_state.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-15 15:49:48 -04:00
Eric Anholt
57de9bbb63 vc4: Fix the uniform debug output.
I dropped the shader index when moving to the compiled shader struct, but
didn't update the format string here.
2014-10-15 18:12:03 +01:00
Eric Anholt
201d4c0b2a vc4: Add support for user clip plane and gl_ClipVertex.
Fixes about 15 piglit tests about interpolation and clipping.
2014-10-15 18:11:46 +01:00
Eric Anholt
6a0bf67048 vc4: Move the output semantics setup to a helper.
I want to reuse it elsewhere to set up outputs that aren't in the TGSI.
2014-10-15 18:11:46 +01:00
Kenneth Graunke
39a5a60b57 i965: Allow CSE on Gen4-5 unary math.
Due to the implicit move-from-GRF, unary math looks a lot like the Gen6+
math instruction: it's a single instruction (SEND) with a GRF source.
The difference is that it also implicitly clobbers a message register.

The only visible effect is that CSE will remove the MRF-clobbering from
later math operations.  This should be fine; compute_to_mrf and
remove_redundant_mrf_writes don't look at the values populated by
implied writes, so they can't rely on those values being present.
Less interference may actually help those passes make more progress.

Binary math is still problematic, since it involves a separate MOV
instruction to load the second operand.  We continue disallowing CSE for
binary math operations.

total instructions in shared programs: 3340303 -> 3340100 (-0.01%)
instructions in affected programs:     26927 -> 26724 (-0.75%)
Nothing hurt, gained, or lost.  ~6% reduction on a few shaders.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-10-15 08:44:54 -07:00
Michel Dänzer
159f93cf39 r600g,radeonsi: Only set use_staging_texture = TRUE once
No need to check for setting the flag after we set it already.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-10-15 16:26:30 +09:00
Michel Dänzer
87da286755 r600g,radeonsi: Use staging texture for transfers if any miplevel is tiled
We set the NO_CPU_ACCESS flag for BO allocation in that case, so direct CPU
access may not work.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-10-15 16:26:14 +09:00
Michel Dänzer
3ede67a4c6 winsys/radeon: Use separate caching buffer manager for each set of flags
Otherwise the caching buffer manager may return a buffer which was created
with a different set of flags, which can cause trouble.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-10-15 16:11:40 +09:00
Andres Gomez
657764c21c configure.ac: check for libexpat when no pkg-config is available
Previously, when no pkg-config was available for
libexpat we would just add the needed linking
flags without any extra check.

Now, we check that the library and the headers are
also installed in the building environment.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-10-15 08:59:12 +02:00
Tom Stellard
8cf6482c3d clover: Fix regression in module serialization
We need to serialize semantic information for arguments, which was added
in 06139c56fa.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-10-14 17:58:06 -04:00
Jason Ekstrand
3435aa49f4 i965/fs: Use the correct regs_written on unspill instructions
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-14 12:39:45 -07:00
Ilia Mirkin
742158b51e st/gbm: fix order of arguments passed to is_format_supported
Reported by Coverity

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2014-10-14 12:33:38 -04:00
Ilia Mirkin
5524af8136 nouveau: 3d textures are unsupported, limit 3d levels to 1
Ideally there would be a swrast fallback, but the driver isn't ready for
that. This should avoid crashes if someone tries to use 3d textures
though.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: mesa-stable@lists.freedesktop.org
2014-10-14 12:33:38 -04:00
Rob Clark
abe3b3d1e0 freedreno: use tgsi_lowering
Now that the freedreno_lowering code is moved to tgsi_lowering, remove
our private copy and switch over to using the common version.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-10-14 12:30:08 -04:00
David Heidelberger
d2c1d9693f r300/compiler: remove useless check
This code is already in if (!variable->C->is_r500) so no need check
twice.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: David Heidelberger <david.heidelberger@ixit.cz>
2014-10-14 12:18:32 -04:00
Nick Sarnie
e5bf8d38db ilo: Build pipe-loader for ilo
Trivial patch to create the pipe loader for ilo. All the code was already there.

Signed-off-by: Nick Sarnie <commendsarnex@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-10-14 16:16:08 +01:00
Emil Velikov
af897df508 automake: explicitly set TARGET_RADEON_{WINSYS,COMMON}
Originally the variables were set only once via the ?= operator but
that causes issues when doing incremental builds. They appear to be
undefined and missing from the dependency list despite their addition
to LIBADD.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84807
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-10-14 16:16:08 +01:00
Eric Anholt
a2d8b6dbd5 vc4: Fix render target NPOT alignment at small miplevels.
The texturing hardware takes the POT level 0 width/height and minifies
those.  This is different from what we were doing, for example, for
273-wide's level 5: POT(273>>5) == 8, while POT(273)>>5 == 16.

Fixes piglit-depthstencil-render-miplevels 273.
2014-10-14 14:57:50 +01:00
Eric Anholt
b5fc9d5664 vc4: Add support for having 0 vertex elements used.
You have to load at least 1, according to the simulator.  Fixes 4 piglit
tests and even more ES2 conformance tests.
2014-10-14 11:29:48 +01:00
Vinson Lee
a2fd55cfb6 auxilary/os: Add DragonFly BSD support in os_get_total_physical_memory.
This patch fixes this build error on DragonFly BSD.

  CC       os/os_misc.lo
os/os_misc.c: In function 'os_get_total_physical_memory':
os/os_misc.c:132:2: error: #error Unsupported *BSD

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-10-13 23:40:46 -07:00
Daniel Manjarres
291be28476 glx: Fix glxUseXFont for glxWindow and glxPixmaps
The current implementation of glxUseXFont requires creating
a temporary pixmap and graphics context, which requires a real
old-school X11 Window, not a glxDrawable. This patch changes
things so that glxUseXFont will also accept a glxWindow or
glxPixmap, and lookup the underlying X11 Drawable. Without
this patch glxUseXFont generates a giant stream of Xerrors
about bad drawables and bad graphics contexts.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54372

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-10-13 22:05:58 -06:00