fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-03 07:10:15 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965: Make brw_texture_offset() not use ir_texture.

Browse source 
Our new IR won't have ir_texture objects.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
This commit is contained in:
Connor Abbott 2014-08-04 15:20:38 -07:00 • committed by Kenneth Graunke
parent a71455bc99
commit fa212c6b98
4 changed files with 15 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
View file

@ -1944,7 +1944,9 @@ fs_visitor::visit(ir_texture *ir)
* use offset_value.file to distinguish between no offset, a constant
* offset, and a non-constant offset.
*/
offset_value = fs_reg(brw_texture_offset(ctx, const_offset));
offset_value =
fs_reg(brw_texture_offset(ctx, const_offset->value.i,
const_offset->type->vector_elements));
} else {
ir->offset->accept(this);
offset_value = this->result;

13
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -358,18 +358,15 @@ brw_math_function(enum opcode op)
}
uint32_t
brw_texture_offset(struct gl_context *ctx, ir_constant *offset)
brw_texture_offset(struct gl_context *ctx, int *offsets,
unsigned num_components)
{
/* If the driver does not support GL_ARB_gpu_shader5, the offset
* must be constant.
*/
assert(offset != NULL || ctx->Extensions.ARB_gpu_shader5);
assert(offsets != NULL || ctx->Extensions.ARB_gpu_shader5);
if (!offset) return 0; /* nonconstant offset; caller will handle it. */
signed char offsets[3];
for (unsigned i = 0; i < offset->type->vector_elements; i++)
offsets[i] = (signed char) offset->value.i[i];
if (!offsets) return 0; /* nonconstant offset; caller will handle it. */
/* Combine all three offsets into a single unsigned dword:
*
@ -378,7 +375,7 @@ brw_texture_offset(struct gl_context *ctx, ir_constant *offset)
* bits 3:0 - R Offset (Z component)
*/
unsigned offset_bits = 0;
for (unsigned i = 0; i < offset->type->vector_elements; i++) {
for (unsigned i = 0; i < num_components; i++) {
const unsigned shift = 4 * (2 - i);
offset_bits |= (offsets[i] << shift) & (0xF << shift);
}

3
src/mesa/drivers/dri/i965/brw_shader.h
View file

@ -182,7 +182,8 @@ public:
virtual void invalidate_live_intervals() = 0;
};
uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
uint32_t brw_texture_offset(struct gl_context *ctx, int *offsets,
unsigned num_components);
#endif /* __cplusplus */

7
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View file

@ -2552,8 +2552,11 @@ vec4_visitor::visit(ir_texture *ir)
vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, opcode);
if (ir->offset != NULL)
inst->texture_offset = brw_texture_offset(ctx, ir->offset->as_constant());
if (ir->offset != NULL && !has_nonconstant_offset) {
inst->texture_offset =
brw_texture_offset(ctx, ir->offset->as_constant()->value.i,
ir->offset->type->vector_elements);
}
/* Stuff the channel select bits in the top of the texture offset */
if (ir->op == ir_tg4)