We only want the atomic bit to be conditional to non sparse.
Also take the opportunity to fix buffer features and report the same
supported atomic formats as images.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ed77f67e44 ("anv: add emulated 64bit integer storage support")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35358>
PresentWait2 should be possible on any physical device, as it adds a
surface capability query that depends on common wsi code.
Signed-off-by: Derek Foreman <derek.foreman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35414>
Helped from: Stéphane Cerveau <scerveau@igalia.com>
- Fix crash when segmentation is unavailable
- Set 8x8 to minCodedExtent
- Fix typo for GOLDEN and ALTREF scale factor
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35485>
Don't report compressed memory type in the case of Xe2 modifiers
as the Vulkan spec requires identical memory types behind the
VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
Instead, we require dedicated allocation to get the right
compressed memory in allocation stage. The BMG modifier also
requires scanout flag to set. Refer to comments.
Thanks for the help from:
Nanley Chery <nanley.g.chery@intel.com>
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke <kenneth@whitecape.org>
and other people not listed.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
When aux has to be disabled (ISL_SURF_USAGE_DISABLE_AUX_BIT)
for some reasons like VK_SHARING_MODE_CONCURRENT, we simply
cannot implicitly choose any modifier with compression.
Otherwise, we run into a situation that an image is created
with a modifier but without the aux support that modifier
requires. It will fail a CTS test once Xe2 modifiers are
enabled:
dEQP-VK.wsi.wayland.swapchain.private_data.image_sharing_mode
MESA: warning: ../src/intel/vulkan/anv_image.c:1198: image with
modifier unexpectedly has wrong aux usage (VK_ERROR_UNKNOWN)
GFX12.x (MTL) does not show this failure because only one queue
family is present. But they will face the same issue when aux is
disabled for any other reasons:
NotSupported (Only 1 queue families available for
VK_SHARING_MODE_CONCURRENT at vktWsiSwapchainTests.cpp:715)
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
As a part of the effort to unify the displayable attribute
on dmabuf sharing across drivers, we set scanout flag on
imported bos on Xe2+.
Refer to the comment in the change.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
Narrow down the definition of two compression flags suggested by
Nanley Chery <nanley.g.chery@intel.com> so that we can address
the unified compression support of Xe2 modifiers and don't have
to set media compression flag thats result more update in the
stack.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
For pre-merge pipelines, we know that we don't need to run the
container-check jobs unless image-tags.yml has been modified. In this
case, we can just skip the container jobs, because we 'know' that the
containers are present in the upstream repo.
For downstream or off-main pipelines, we still need to run the check
job, because the changed-file tracking is not reliable on other
branches, and because we may need to copy the container image from the
upstream container storage into the user's namespace.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35203>
Update the device info output to display EU count together with the native
SIMD width. This clarifies the SIMD width of execution units and explains
differences in EU counts between hardware generations.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35116>
Source: BSpec "Instruction Fields" page (56701), SWSB field.
Credits to Caio Oliveira here, since he was helping me while we found
this issue together.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35395>
Simplify transition_depth_buffer() by reusing a function to update the
fast-clear value instead of open-coding that logic.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35329>
Use get_copy_format_for_bpb() instead of
get_ccs_compatible_uint_format() when performing blorp_copy(). This
matches the code path taken on gfx20 and increases the testing of cases
which would impact gfx12.0 in isl_get_sampler_clear_field_offset().
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35329>
Through testing, I've found that the sampler will fetch the clear color
pixel from the converted clear color field in more cases. So, stop
reporting the raw dword offset for them:
* On gfx12.5, for 32-bpc color images.
* On gfx11-12.0, for 64-bpp color images.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35329>
This would cause Mesa to print this message even if an Intel GPU is just
being enumerated by a Vulkan application. For example, `vulkaninfo
--summary`.
Fixes: 52f73db5b7 ("brw: implement read without format lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35396>
Prior to Gen 11, we had to upload a bunch of SGVs
(FirstVertex, BaseVertex, BaseInstance, DrawID) via
3DSTATE_VERTEX_BUFFERS.
For Gen11+, we upload via 3DSTATE_SGVS_2 instead.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35376>
The intention here is to build a SIMD8 value, that will be expanded
as needed -- just like the SHL/ADD case, but with a single instruction.
Found when the was triggering invalid MAD with SIMD32 (that gets compressed)
*and* with overlapping destination and source *and* which would cause
conflict when divided into two SIMD16.
Fixes: 338273dedd ("brw/reg_allocate: Optimize spill offset calculation using integer MAD")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35302>
Load the format enum and then just go through a series of :
if format == R16G16B16A16_UNORM
color = lower_r32g32_uint_tor_r16g16b16a16_unorm(color)
else if format == R16G16B16A16_SNORM
...
For Gfx12.5, there is no in-shader conversion.
For Gfx12/11, the in-shader conversion covers the following formats :
- ISL_FORMAT_R10G10B10A2_UNORM
- ISL_FORMAT_R10G10B10A2_UINT
- ISL_FORMAT_R11G11B10_FLOAT
For Gfx9, the following formats :
- ISL_FORMAT_R16G16B16A16_UNORM
- ISL_FORMAT_R16G16B16A16_SNORM
- ISL_FORMAT_R10G10B10A2_UNORM
- ISL_FORMAT_R10G10B10A2_UINT
- ISL_FORMAT_R8G8B8A8_UNORM
- ISL_FORMAT_R8G8B8A8_SNORM
- ISL_FORMAT_R16G16_UNORM
- ISL_FORMAT_R16G16_SNORM
- ISL_FORMAT_R11G11B10_FLOAT
- ISL_FORMAT_R8G8_UNORM
- ISL_FORMAT_R8G8_SNORM
- ISL_FORMAT_R16_UNORM
- ISL_FORMAT_R16_SNORM
- ISL_FORMAT_R8_UNORM
- ISL_FORMAT_R8_SNORM
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22524>
On ANV the vkCmdBeginRendering function was hard coded to use
VK_IMAGE_ASPECT_COLOR_BIT for all color attachments, instead of using
the aspect bit specified when the vkImageView was initialized, which
made it impossible for applications to render to views of multi-planar
formats like VK_FORMAT_G8_B8R8_2PLANE_420_UNORM correctly.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13221
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35340>
0e3e5146cf ("intel/brw: Use correct instruction for value change check
when coalescing") enabled some new cases that exposed a pre-existing
bug that would turn something like this :
mul.sat(16) %789:F, %787:F, %788:F
mov.g.f0.0(16) %790:F, %789:F
(+f0.0) sel(16) %800:UD, %790:UD, 0u
into this :
mul.sat(16) %790:F, %787:F, %788:F
mov.g.f0.0(16) null:F, null<8,8,1>:F
(+f0.0) sel(16) %800:UD, %790:UD, 0u
The mov[] array can contain the same instruction because it's repeated
for each REG_SIZE writes and a SIMD16 instruction will write 2
REG_SIZE.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0e3e5146cf ("intel/brw: Use correct instruction for value change check when coalescing")
Cc: mesa-stable
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35276>
There's always only the ARF scalar register source, so don't
bother printing other information that won't be used. Matches
the assembler code.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35297>
