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brw: enable more lowering for bitfield manipulation at non 32bit sizes

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35381>
This commit is contained in:
Lionel Landwerlin 2025-06-03 18:11:43 +03:00 • committed by Marge Bot
parent d983280da9
commit 1d8382b88e
2 changed files with 7 additions and 1 deletions
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6
src/intel/compiler/brw_compiler.c
View file

@ -46,6 +46,8 @@ const struct nir_shader_compiler_options brw_scalar_nir_options = {
.has_uclz = true,
.lower_base_vertex = true,
.lower_bitfield_extract = true,
.lower_bitfield_extract8 = true,
.lower_bitfield_extract16 = true,
.lower_bitfield_insert = true,
.lower_device_index_to_zero = true,
.lower_fdiv = true,
@ -115,7 +117,9 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
nir_lower_find_lsb64 |
nir_lower_ufind_msb64 |
nir_lower_bit_count64 |
nir_lower_iadd3_64;
nir_lower_iadd3_64 |
nir_lower_bitfield_extract64 |
nir_lower_bitfield_reverse64;
nir_lower_doubles_options fp64_options =
nir_lower_drcp |
nir_lower_dsqrt |

2
src/intel/compiler/brw_nir.c
View file

@ -1072,6 +1072,8 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data)
* fewer MOV instructions.
*/
switch (alu->op) {
case nir_op_bitfield_reverse:
return alu->def.bit_size != 32 ? 32 : 0;
case nir_op_idiv:
case nir_op_imod:
case nir_op_irem: