Commit graph

51454 commits

Author SHA1 Message Date
Marek Olšák
e773a48a3b r600g: fix uploading non-zero mipmap levels of depth textures
This fixes piglit/depth-level-clamp.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:31 +02:00
Marek Olšák
fe1fd67556 r600g: don't flush depth textures set as colorbuffers
The only case a depth buffer can be set as a color buffer is when flushing.

That wasn't always the case, but now this code isn't required anymore.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:31 +02:00
Marek Olšák
6842d5fced r600g: don't set dirty_db_mask for a flushed depth texture
A flush depth texture is never set as a depth buffer and never flushed.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:31 +02:00
Marek Olšák
5a17d8318e r600g: flush depth textures bound to vertex shaders
This was missing/broken. There are also minor code cleanups.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:31 +02:00
Marek Olšák
dee58f94af r600g: do fine-grained depth texture flushing
- maintain a mask of which mipmap levels are dirty (instead of one big flag)
- only flush what was requested at a given point and not the whole resource
  (most often only one level and one layer has to be flushed)

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
df79eb5956 r600g: remove is_flush from DSA state
we can just update the state when decompressing, there's no need to add
additional info into the DSA state

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
43e3f19c76 r600g: set DISABLE in CB_COLOR_CONTROL if colormask is 0
this will be useful for in-place DB decompression, otherwise should be harmless

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
4fe74412cf r600g: move CB_SHADER_MASK setup into cb_misc_state
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
a1a1ff5ec0 r600g: move MULTIWRITE setup into cb_misc_state for r6xx-r7xx
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
0ea76916e6 r600g: move CB_TARGET_MASK setup into new cb_misc_state
to remove some overhead from draw_vbo. This is a derived state.

BTW, I've got no idea how compute interacts with 3D here, but it should
use cb_misc_state, so that 3D and compute don't conflict.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
5ba15d8d38 st/mesa: implement accelerated stencil blitting using shader stencil export
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
a7f3697eb8 st/mesa: set colormask to zero when blitting depth
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
5a74e17ab0 gallium/u_blit: remove useless memset calls
the structure is calloc'd.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
24e0a26335 gallium/u_blit: drop not-very-useful wrapper around util_blit_pixels_writemask
just rename it to util_blit_pixels

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
3f13b5da15 gallium/u_blit: don't do two copies for non-2D textures
Because u_blit couldn't sample a 1D, 3D, CUBE and ARRAY texture, we created
a 2D texture holding a copy of one slice of the source texture (even for 1D).

Let's just do it right.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
2dca61bcb3 gallium/util: move pipe_tex_to_tgsi_tex helper function into u_inlines
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
bdaf0a085b gallium/u_blitter: accelerate stencil-only copying
This doesn't seem to be used by anything yet, but better safe than sorry.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
12fd81f9e7 gallium/u_blitter: accelerate depth-stencil copying using shader stencil export
This fixes stencil buffer write transfers on r600g.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
76db2c121c gallium: add util_format_stencil_only helper function
used for stencil sampler views.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
a730838a42 gallium/u_blitter: minify depth0 when initializing last_layer
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
91cf9fe988 gallium/u_gen_mipmap: accelerate depth texture mipmap generation
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
13b0af721a mesa: remove assertions that do not allow compressed 2D_ARRAY textures
NOTE: This is a candidate for the 8.0 branch.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Paul Berry
33202b4876 i965/msaa: Enable CMS layout on Gen7 for the formats that support it.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:50 -07:00
Paul Berry
4ebbc76621 i965/msaa: Add CMS support to blorp.
This patch updates the blorp engine to properly handle the case where
the surface being textured from uses Gen7's CMS MSAA layout.  The
following changes were necessary:

- Before reading color values from the surface, we need to read from
  the MCS buffer using the ld_mcs sampler message.  This is done by
  the mcs_fetch() function, and the result is stored in the mcs_data
  register.  This only needs to be done once per pixel, since the MCS
  value is shared between all samples belonging to a pixel.

- When reading color values from the surface, we need to use the
  ld2dms sampler message instead of the ld2dss message, and we need to
  provide the value read from the MCS buffer as an argument.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
754953693d i965/msaa: Add CMS-related sampler messages to brw_defines.h.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
7b3263af69 i965/msaa: Set SURFACE_STATE properly when CMS MSAA is in use.
When a buffer using Gen7's CMS MSAA layout is bound to a texture or a
render target, the SURFACE_STATE structure needs to point to the MCS
buffer and to indicate its pitch.  This patch updates the functions
that emit SURFACE_STATE to handle CMS layout properly.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
0ba813506d i965/msaa: Add CMS MSAA settings to brw_structs.h.
Previously the DWORD used to control the CMS MSAA layout was just a
pad value, because we didn't use it.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
ccae1b1cd7 i965/msaa: Allocate MCS buffer when CMS MSAA is in use.
To implement Gen7's CMS MSAA layout, we need an extra buffer, the MCS
(Multisample Control Surface) buffer.  This patch introduces code for
allocating and deallocating the buffer, and storing a pointer to it in
the intel_mipmap_tree struct.

No functional change, since the CMS layout is not enabled yet.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
1bd4d456cd i965/msaa: Add an enum to describe MSAA layout.
From the Ivy Bridge PRM, Vol 1 Part 1, p112:

    There are three types of multisampled surface layouts designated
    as follows:
      - IMS Interleaved Multisampled Surface
      - CMS Compressed Mulitsampled Surface
      - UMS Uncompressed Multisampled Surface

Previously, the i965 driver only used IMS and UMS formats, and
distinguished beetween them using the boolean
intel_mipmap_tree::msaa_is_interleaved.  To facilitate adding support
for the CMS format, this patch replaces that boolean (and other
booleans derived from it) with an enum
INTEL_MSAA_LAYOUT_{IMS,CMS,UMS}.  It also updates the terminology used
in comments throughout the driver to match the IMS/CMS/UMS terminology
used in the PRM.  CMS layout is not yet used.

The enum has a fourth possible value, INTEL_MSAA_LAYOUT_NONE, which is
used for non-multisampled surfaces.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
67b0f7c7dd i965/msaa: Move {rt,tex}_interleaved into blorp program key.
On Gen6, MSAA buffers always use an interleaved layout and non-MSAA
buffers always use a non-interleaved layout, so it is not strictly
necessary to keep track of the layout of the texture and render target
surfaces in the blorp program key.  However, it is cleaner to do so,
since (a) it makes the blorp compiler less dependent on implicit
knowledge about how the GPU pipeline is configured, and (b) it paves
the way for implementing compressed multisampled surfaces in Gen7.

This patch won't cause any redundant compiles, because the layout of
the texture and render target surfaces depends on other parameters
that are already in the blorp program key.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Kristian Høgsberg
2adfce4a18 mapi: Move GL_NV_draw_buffers extension to es_EXT.xml
We don't generate public entrypoints for GLES extensions, so move the
GL_NV_draw_buffers definition from ARB_draw_buffers.xml to es_EXT.xml.
When the extension is defined in ARB_draw_buffers.xml, we end up with a
public entry point for it, but no prototype, which gives an error when
compiled with --disable-asm and --disable-shared-glapi.

Instead, just move the GLES extension to es_EXT.xml so this doesn't happen.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2012-07-11 15:28:36 -04:00
Kristian Høgsberg
e6a33570b7 egl: Add EGL_WAYLAND_PLANE_WL attribute
This lets us specify the plane to create the image for for multiplanar
wl_buffers.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2012-07-11 15:28:36 -04:00
Kristian Høgsberg
1aaec8c609 wayland-drm: Add protocol to create planar buffers 2012-07-11 15:28:35 -04:00
Kristian Høgsberg
379eb47ea6 wayland-drm: Pass struct wl_drm_buffer to the driver
We're going to extend this to support multi-plane buffers, so pass this
to the driver so it can access the details.
2012-07-11 15:28:35 -04:00
Kristian Høgsberg
95bc0527e9 intel: Implement __DRIimage::createSubImage and bump supported version to 5
We use the new miptree offset to pick out the sub-image when we bind
the EGLImage to a texture.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2012-07-11 15:28:35 -04:00
Kristian Høgsberg
02ebad900d intel: Add offset field to miptree
This lets us specify an offset into the bo where the miptree starts,
which will let us set up a texture for a single plane in a planar buffer.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-07-11 15:28:35 -04:00
Kristian Høgsberg
44a2b57f93 intel: Add support for new __DRIimage formats 2012-07-11 15:28:34 -04:00
Kristian Høgsberg
c029834808 __DRIimage: version 5, add new formats and createSubImage
The additions in version 5 enables creating EGLImages for different planes
of a YUV buffer.  createImageFromName is still used to create the containing
__DRIimage, and createSubImage can then be used no that __DRIimage to create
__DRIimages that correspond to the y, u, and v planes (__DRI_IMAGE_FORMAT_R8)
or the uv planes (__DRI_IMAGE_FORMAT_RG88) for formats such as NV12 where
the u and v components are interleaved.  Packed formats such as YUYV etc
doesn't require any special treatment, we just sample those as a regular
ARGB texture.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2012-07-11 15:28:34 -04:00
Tom Stellard
c0f7fe7b79 r600g/compute: Disable growing the memory pool
The code for growing the memory pool (which is used for storing all of
the global buffers) wasn't working.  There seem to be two separate issues
with the memory pool code.  The first was the way it was growing the pool.
When the memory pool needed more space, it would:

1. Copy the data from the memory pool's backing texture to system memory.
2. Delete the memory pool's texture
3. Create a bigger backing texture for the memory pool.
4. Copy the data from system memory into the bigger texture.

The copy operations didn't seem to be working, and I suspect that since
they were using fragment shaders to do the copy, that there might have
been a problem with the mixing of compute and 3D state.

The other issue is that the size of 1D textures is limited, and I was
having trouble getting 2D textures to work.

I think these problems will be easier to solve once more code is shared
between 3D and compute, which is why I decided to disable it for now
rather than continue searching for a fix.
2012-07-11 17:53:54 +00:00
Tom Stellard
49ae102ee3 radeon/llvm: Use multiclasses for floating point loads
The original strategy for handling floating point loads, which was to
lower (f32 load) to (f32 bitcast (i32 load)) wasn't really working.  The
main problem was that the DAG legalizer couldn't handle replacing a node
with two results (load) with a node with only one result (bitcast).
2012-07-11 17:47:20 +00:00
Tom Stellard
bbdf3af857 radeon/llvm: Don't set the IMM bit in SMRD instruction definitions.
The IMM bit is already being set in SICodeEmitter.
2012-07-11 17:47:20 +00:00
Tom Stellard
d36499aa62 r600g/compute: Add more debugging output 2012-07-11 17:46:59 +00:00
Eric Anholt
f9b3e257d1 i965: Revert the VBOs-in-system-memory hack.
It didn't change performance on Lightsmark or Nexuiz, which both used
DYNAMIC_DRAW buffers, but it was killing performance (40% CPU wasted pwriting
buffers) on a closed-source app we're looking at.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-11 09:20:21 -07:00
Eric Anholt
b5c037f6b1 Add emacs setup for the docs/devinfo.html comment wrapping recommendation.
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-07-11 09:20:21 -07:00
Ian Romanick
a8724d85f8 glx/dri2: Add support for GLX_ARB_create_context_robustness
Add the infrastructure required for this extension.  There is no
xserver support and no driver support yet.  Drivers can enable this be
advertising DRI2 version 4 and accepting the
__DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS flag and the
__DRI_CTX_ATTRIB_RESET_STRATEGY attribute in create context.

Some additional Mesa infrastructure is needed before drivers can do
this.  The GL_ARB_robustness spec, which all Mesa drivers already
advertise, requires:

    "If the behavior is LOSE_CONTEXT_ON_RESET_ARB, a graphics reset
    will result in the loss of all context state, requiring the
    recreation of all associated objects."

It is necessary to land this infrastructure now so that the related
infrastructure can land in the xserver.  The xserver has very long
release schedules, and the remaining Mesa parts should land long, long
before the next xserver merge window opens.

v2: Expose robustness as a DRI2 extension rather than bumping
__DRI_DRI2_VERSION.

v3: Add a comment explaining why dri2->base.version >= 3 is also
required for GLX_ARB_create_context_robustness.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-07-11 08:54:50 -07:00
Ian Romanick
de9ed51525 dri2: Hard-code the DRI2 version
This allows revising the dri_interface.h separately from adding driver
support.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-11 08:54:50 -07:00
Ian Romanick
2879f758b5 glapi: Apply Xorg indent rules to all files generated for the xserver
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-11 08:54:50 -07:00
Kenneth Graunke
a0698b000b docs: Update GL3.txt.
We neglected to list the deprecation model/forward compatible context
support.

inverse() has been done for a while.

None of us know what "highp change" means; GLSL 1.30 already added the
ability to recognize precision keywords, and it doesn't look like 1.40
has any new requirements there (precision keywords still have no meaning).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2012-07-10 16:53:49 -07:00
Chad Versace
551078bb62 mesa: Remove unneeded extern qualifiers
Remove 'extern' from the functions declared in texcompress_etc.h.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-10 16:51:19 -07:00
Vadim Girlin
3770847960 r600g: improve flushed depth texture handling v2
Use r600_resource_texture::flished_depth_texture for GPU access, and
allocate it in the VRAM. For transfers we'll allocate texture in the GTT
and store it in the r600_transfer::staging.

Improves performance when flushed depth texture is frequently used by the
GPU, e.g. in Lightsmark (~30%)

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-07-11 02:39:59 +04:00