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radeon/llvm: Use multiclasses for floating point loads
The original strategy for handling floating point loads, which was to lower (f32 load) to (f32 bitcast (i32 load)) wasn't really working. The main problem was that the DAG legalizer couldn't handle replacing a node with two results (load) with a node with only one result (bitcast).
This commit is contained in:
Tom Stellard
parent
bbdf3af857
commit
49ae102ee3
7 changed files with 46 additions and 50 deletions
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@ -33,9 +33,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FEXP2, MVT::f32, Legal);
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setOperationAction(ISD::FRINT, MVT::f32, Legal);
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setOperationAction(ISD::LOAD, MVT::f32, Custom);
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setOperationAction(ISD::LOAD, MVT::v4f32, Custom);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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@ -47,7 +44,6 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
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switch (Op.getOpcode()) {
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default: return AMDILTargetLowering::LowerOperation(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::LOAD: return BitcastLOAD(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
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}
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@ -130,36 +126,6 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
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OneSubAC);
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}
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/// BitcastLoad - Convert floating point loads to integer loads of the same
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/// type width and the bitcast the result back to a floating point type.
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SDValue AMDGPUTargetLowering::BitcastLOAD(SDValue Op, SelectionDAG &DAG) const
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{
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DebugLoc DL = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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EVT IntVT;
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if (VT == MVT::f32) {
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IntVT = MVT::i32;
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} else if (VT == MVT::v4f32) {
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IntVT = MVT::v4i32;
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} else {
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return Op;
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}
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LoadSDNode * LD = dyn_cast<LoadSDNode>(Op);
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assert(LD);
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SDValue NewLoad = DAG.getLoad (LD->getAddressingMode(),
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LD->getExtensionType(), IntVT, DL,
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LD->getChain(), LD->getBasePtr(),
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LD->getOffset(), IntVT,
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LD->getMemOperand());
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SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT, NewLoad);
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DAG.ReplaceAllUsesWith(Op.getValue(0).getNode(), &Bitcast);
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return Op;
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}
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SDValue AMDGPUTargetLowering::LowerSELECT_CC(SDValue Op,
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SelectionDAG &DAG) const
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{
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@ -23,7 +23,6 @@ class AMDGPUTargetLowering : public AMDILTargetLowering
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{
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private:
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue BitcastLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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@ -203,9 +203,12 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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emit(inst);
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break;
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}
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case AMDGPU::VTX_READ_PARAM_eg:
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case AMDGPU::VTX_READ_GLOBAL_eg:
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case AMDGPU::VTX_READ_GLOBAL_128_eg:
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case AMDGPU::VTX_READ_PARAM_i32_eg:
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case AMDGPU::VTX_READ_PARAM_f32_eg:
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case AMDGPU::VTX_READ_GLOBAL_i32_eg:
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case AMDGPU::VTX_READ_GLOBAL_f32_eg:
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case AMDGPU::VTX_READ_GLOBAL_v4i32_eg:
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case AMDGPU::VTX_READ_GLOBAL_v4f32_eg:
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{
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uint64_t InstWord01 = getBinaryCodeForInstr(MI);
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uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
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@ -253,7 +253,7 @@ void R600TargetLowering::lowerImplicitParameter(MachineInstr *MI, MachineBasicBl
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.addReg(AMDGPU::ALU_LITERAL_X)
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.addImm(dword_offset * 4);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::VTX_READ_PARAM_eg))
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::VTX_READ_PARAM_i32_eg))
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.addOperand(MI->getOperand(0))
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.addReg(PtrReg)
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.addImm(0);
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@ -1021,14 +1021,6 @@ class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
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let DATA_FORMAT = 0xD; // COLOR_32
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}
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def VTX_READ_PARAM_eg : VTX_READ_32_eg <0,
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[(set (i32 R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
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>;
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def VTX_READ_GLOBAL_eg : VTX_READ_32_eg <1,
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[(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
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>;
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class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
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: VTX_READ_eg <buffer_id, (outs R600_Reg128:$dst), pattern> {
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@ -1040,10 +1032,40 @@ class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
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let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
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}
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def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
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[(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
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//===----------------------------------------------------------------------===//
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// VTX Read from parameter memory space
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//===----------------------------------------------------------------------===//
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class VTX_READ_PARAM_32_eg <ValueType vt> : VTX_READ_32_eg <0,
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[(set (vt R600_TReg32_X:$dst), (load_param ADDRVTX_READ:$ptr))]
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>;
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def VTX_READ_PARAM_i32_eg : VTX_READ_PARAM_32_eg<i32>;
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def VTX_READ_PARAM_f32_eg : VTX_READ_PARAM_32_eg<f32>;
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//===----------------------------------------------------------------------===//
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// VTX Read from global memory space
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//===----------------------------------------------------------------------===//
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// 32-bit reads
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class VTX_READ_GLOBAL_eg <ValueType vt> : VTX_READ_32_eg <1,
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[(set (vt R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))]
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>;
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def VTX_READ_GLOBAL_i32_eg : VTX_READ_GLOBAL_eg<i32>;
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def VTX_READ_GLOBAL_f32_eg : VTX_READ_GLOBAL_eg<f32>;
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// 128-bit reads
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class VTX_READ_GLOBAL_128_eg <ValueType vt> : VTX_READ_128_eg <1,
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[(set (vt R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))]
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>;
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def VTX_READ_GLOBAL_v4i32_eg : VTX_READ_GLOBAL_128_eg<v4i32>;
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def VTX_READ_GLOBAL_v4f32_eg : VTX_READ_GLOBAL_128_eg<v4f32>;
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}
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let Predicates = [isCayman] in {
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@ -468,5 +468,10 @@ multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass,
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>;
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}
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multiclass SMRD_32 <bits<5> op, string asm, RegisterClass dstClass> {
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defm _F32 : SMRD_Helper <op, asm, dstClass, f32>;
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defm _I32 : SMRD_Helper <op, asm, dstClass, i32>;
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}
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include "SIInstrFormats.td"
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include "SIInstructions.td"
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@ -358,7 +358,8 @@ def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORM
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//def TBUFFER_STORE_FORMAT_XYZ : MTBUF_ <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", []>;
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//def TBUFFER_STORE_FORMAT_XYZW : MTBUF_ <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", []>;
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defm S_LOAD_DWORD : SMRD_Helper <0x00000000, "S_LOAD_DWORD", SReg_32, f32>;
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defm S_LOAD_DWORD : SMRD_32 <0x00000000, "S_LOAD_DWORD", SReg_32>;
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//def S_LOAD_DWORDX2 : SMRD_DWORDX2 <0x00000001, "S_LOAD_DWORDX2", []>;
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defm S_LOAD_DWORDX4 : SMRD_Helper <0x00000002, "S_LOAD_DWORDX4", SReg_128, v4i32>;
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defm S_LOAD_DWORDX8 : SMRD_Helper <0x00000003, "S_LOAD_DWORDX8", SReg_256, v8i32>;
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