Commit graph

70222 commits

Author SHA1 Message Date
Ilia Mirkin
9143940da2 gm107/ir: add lane/vertex count sysvals
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-04-27 21:25:29 -04:00
Ilia Mirkin
89e0b08794 gk110/ir: add support for writing per-patch and shader outputs
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-04-27 21:25:28 -04:00
Ilia Mirkin
52614f59b7 freedreno/a3xx: color masking works like a blend for some formats
When there is a colormask active that does not cover all the channels,
enable reading in the destination like with a combining blend
operation. This fixes fbo-blending-formats on a3xx.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-04-27 20:17:07 -04:00
Ilia Mirkin
9fc3f47278 freedreno/a3xx: add support for S8 and Z32F_S8
Enables ARB_depth_buffer_float. There is no sampling support for
interleaved Z32F_S8, so we store the two textures separately, one as
Z32F, the other as S8. As a result, we need a lot of additional logic
for restores and transfers.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-04-27 20:17:07 -04:00
Ilia Mirkin
1571da6ac3 freedreno/a3xx: add Z32F support
32-bit depth buffers are stored as unorm, and thus need special handling
when moving to and from gmem. They are copied into gmem by writing
depth, and resolved from gmem using a special resolve bit which
apparently float-ifies the data.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-04-27 20:17:07 -04:00
Ilia Mirkin
0a4cb00c77 freedreno: add fd_transfer to wrap around pipe_transfer
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-04-27 20:17:07 -04:00
Ilia Mirkin
f5c1101996 freedreno/a3xx: add support for disabling depth clipping
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-04-27 20:17:07 -04:00
Kenneth Graunke
dffc1a0ae3 i965/vs: Remove unnecessary NULL check on generate_code() result.
Code generation is not allowed to fail for any reason - in fact,
fs_generator has no mechanism for failing.  The visitor is responsible
for that.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-27 14:59:06 -07:00
Timothy Arceri
d795cc6508 glsl: fix packing support for arrays of doubles
Broke in commit f00c5f85b8 when
adding support for multidimensional arrays

Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
2015-04-28 07:49:32 +10:00
Matt Turner
ff6ee39c19 i965: Enable ARB_gpu_shader5 on Gen8+.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-27 14:44:32 -07:00
Matt Turner
0c06d019bc i965/fs: Fix code emission for imul_high in NIR.
Copy over from brw_fs_visitor.cpp.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-27 14:44:32 -07:00
Matt Turner
ecf428aa59 i965/fs: Fix stride for multiply in macro.
We have to use W/UW type for src1 of the multiply in the MUL/MACH macro,
but in order to read the low 16-bits of each 32-bit integer, we need to
set the appropriate stride.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-27 14:44:32 -07:00
Matt Turner
b3e29a2022 Revert "i965/fs: Allow SIMD16 borrow/carry/64-bit multiply on Gen > 7."
This reverts commit 9f5e5bd34d.

I have no idea what made me believe these didn't apply to Gen > 7. They
do, and without them we generate bad code that causes failures on Gen 8.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-27 14:44:32 -07:00
Olivier Pena
b94a4e8498 scons: Support LLVM 3.5 and 3.6 on windows.
llvm/Config/llvm-config.h is parsed instead of llvm/Config/config.h for
detecting LLVM version
(http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-June/073707.html).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-04-27 21:47:27 +01:00
Ilia Mirkin
dfb0b36e8f mesa: fix up GLSL version when computing GL version
In some situations it is convenient for a driver to expose a higher GLSL
version while some extensions are still incomplete. However in that
situation, it would report a GLSL version that was higher than the GL
version. Avoid that situation by limiting the GLSL version to the GL
version.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-04-27 16:03:16 -04:00
Roland Scheidegger
7c3d1c132e softpipe: fix another stencil-as-float issue
Hopefully this is the last one now (for texture X32_S8X24_UINT views).
+4 piglits.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90167

Reviewed-by: Brian Paul <brianp@vmware.com>
2015-04-27 18:51:30 +02:00
Ilia Mirkin
dfb274af4c mesa: the function name appears to have a gl prefix already
Currently we're producing errors like

User error: GL_INVALID_OPERATION in glglDeleteProgramsARB(invalid call)

And noop_warn appears to be called with the full function name. Don't
prepend a gl prefix.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-04-27 12:06:54 -04:00
Zoë Blade
05e7f7f438 Fix a few typos
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-04-27 17:28:29 +03:00
Francisco Jerez
e17dc004fd i965/gen8: Factor out texture surface state set-up from gen8_update_texture_surface().
This moves most of the surface state set-up logic that can be shared
between textures and shader images to a separate function.
2015-04-27 17:28:29 +03:00
Francisco Jerez
6f26ffaf66 i965/gen7: Factor out texture surface state set-up from gen7_update_texture_surface().
This moves most of the surface state set-up logic that can be shared
between textures and shader images to a separate function.
2015-04-27 17:28:28 +03:00
Francisco Jerez
e94c80c08b i965: Add helper functions to calculate the slice pitch of an array or 3D miptree. 2015-04-27 17:28:28 +03:00
Olivier Pena
f9965347dc scons: add target osmesa using gallium state tracker.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-04-27 15:18:36 +01:00
Marek Olšák
db2415189a radeonsi: set an optimal value for DB_Z_INFO.ZRANGE_PRECISION
Required because of a VI hw bug.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-04-27 15:57:07 +02:00
Marek Olšák
bed98eef9a radeonsi: remove deprecated and useless registers
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-04-27 15:56:27 +02:00
Marek Olšák
393b0e0531 radeonsi: remove useless includes
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-04-27 15:56:27 +02:00
Marek Olšák
d8269be1ce gallium/radeon: print winsys info with R600_DEBUG=info
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-04-27 15:56:27 +02:00
Marek Olšák
96bbdc5188 winsys/radeon: make radeon_bo_vtbl static
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-04-27 15:56:27 +02:00
Timothy Arceri
ca9e280d89 glsl: replace while loop with without_array function
Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-04-27 21:31:08 +10:00
Timothy Arceri
f00c5f85b8 glsl: support packing of arrays of arrays
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-04-27 21:31:01 +10:00
Timothy Arceri
fda5f7bb2f glsl: add arrays of arrays support to without_array function
Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-04-27 21:30:54 +10:00
Martin Peres
9ea38ee96d docs/GL3: started adding support for shader_image_size
Signed-off-by: Martin Peres <martin.peres@linux.intel.com>
2015-04-27 10:13:49 +03:00
Gediminas Jakutis
6fc0cd2f52 gallium/hud: add more options to customize HUD panes
Extends the syntax of GALLIUM_HUD environment variable to:
- Add options to set the size and exact location of each pane.
- Add an option to limit the maximum allowed value of the X axis on a
  pane, clamping the graph down to not go above this value.
- Add an option to auto-adjust the value of the Y axis down to the
  highest value still visible on the graph.

v2:
- Make the patch simpler and smaller.
- With dynamic auto-adjusting on, adjust the Y axis once per pane
  update instead of updating once every several seconds.
- No longer mishandle pane height when having more than one graph per
  pane.
2015-04-26 00:40:08 +02:00
Kenneth Graunke
30c8d8a831 i965: Fill out the rest of brw_debug_recompile_sampler_key().
This makes INTEL_DEBUG=perf report shader recompiles due to CMS vs.
UMS/IMS differences and Sandybridge textureGather workarounds.

Previously, we just flagged them as "Something else".

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-25 09:48:59 -07:00
Kenneth Graunke
19165e3b6e i965: Disassemble sampler message names on Gen5+.
Previously, sampler messages were decoded as

sampler (1, 0, 2, 2) mlen 6 rlen 8              { align1 1H };

I don't know how much time we've collectly wasted trying to read this
format.  I can never recall which number is the surface index, sampler
index, message type, or...whatever that other number is.  Figuring out
the message name from the numerical code is also painful.

Now they decode as:

sampler sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };

This is easy to read at a glance, and matches the format I used for
render target formats.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-04-25 09:47:29 -07:00
Matt Turner
7f5a8ac155 i965/fs: Disallow constant propagation into POW on Gen 6.
Fixes assertion failures in three piglit tests on Gen 6 since commit
0087cf23e.
2015-04-25 02:15:35 -07:00
Ilia Mirkin
67ba388dc0 mesa: add support for exposing up to GL4.2
Add the 4.0/4.1/4.2 extensions lists to compute_version. A couple of
extensions aren't in mesa yet, so those are marked with 0 until they
become supported.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-24 21:55:14 -04:00
Matt Turner
11d2305d7f i965/fs: Add missing pixel_x/y to brw_instruction_name().
Forgotten in commit 529064f6.
2015-04-24 16:25:02 -07:00
Matt Turner
51c61fff8f i965/fs: Don't constant propagate into integer math instructions.
Constant combining won't promote non-floats, so this isn't safe.

Fixes regressions since commit 0087cf23e.
2015-04-24 16:25:02 -07:00
Emil Velikov
e170185896 docs: add news item and link release notes for mesa 10.5.4
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-24 23:00:14 +01:00
Emil Velikov
196cf8db65 docs: Add sha256 sums for the 10.5.4 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit adb47b5b27)
2015-04-24 23:00:14 +01:00
Emil Velikov
5b39cb4736 Add release notes for the 10.5.4 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit ea0d1f575c)
2015-04-24 23:00:14 +01:00
Brian Paul
13b2e6a520 mesa: put more info in glTexImage GL_OUT_OF_MEMORY error message
Give the user some idea about the size of the texture which caused
the GL_OUT_OF_MEMORY error.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-24 14:48:54 -06:00
Matt Turner
0087cf23e8 i965/fs: Allow 2-src math instructions to have immediate src1.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-24 11:39:01 -07:00
Matt Turner
f251ea393b nir: Transform pow(x, 4) into (x*x)*(x*x). 2015-04-24 11:39:01 -07:00
Matt Turner
9b577d5702 glsl: Transform pow(x, 4) into (x*x)*(x*x).
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-24 11:39:01 -07:00
Tapani Pälli
18f44d3030 mesa: fix glGetActiveUniformsiv regression
Commit 7519ddb caused regression to glGetActiveUniformsiv.
Patch adds back validation loop of all given uniforms before
writing any values, not touching params in case of errors
is tested by the conformance suite.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90149
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
2015-04-24 13:42:24 +03:00
Tapani Pälli
a563689a40 mesa: refactor active attrib queries for glGetProgramiv
Main motivation here is to get rid of iterating IR and
encapsulate queries within program resources.
No functional changes.

Piglit tests calling the modified functionality:

   - gl-get-active-attrib-returns-all-inputs
   - glsl-1.50-get-active-attrib-array
   - getactiveattrib

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
2015-04-24 13:41:54 +03:00
Jason Ekstrand
d5a15a89f0 i965: Add an INTEL_DEBUG=spill option to test spilling
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-23 18:08:21 -07:00
Jason Ekstrand
bf55096207 i965/debug: Use the ull specifier for DEBUG enum defines
The INTEL_DEBUG variable is a uint64_t and if we want a enum value higer
than 32 bits, you need to use ull.  We might as well use it for all of them.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-23 18:08:20 -07:00
Kenneth Graunke
5957da1edb i965: Disallow linear blits that are not cacheline aligned.
The BLT engine on Gen8+ requires linear surfaces to be cacheline
aligned.  This restriction was added as part of converting the BLT to
use 48-bit addressing.

The main user, intel_emit_linear_blit, now handles this properly.
But we might also have linear miptrees; just refuse to blit those.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2015-04-23 14:16:57 -07:00