Commit graph

60168 commits

Author SHA1 Message Date
Mike Blumenkrantz
b563bfb4ee zink: add some ci flakes
roundup from recent ci jobs

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23021>
2023-05-15 12:07:16 +00:00
antonino
71107b6dc8 zink: don't create invalid inputs in zink_create_quads_emulation_gs
The helper was creating input locations for some builtin bariables.

This caused validation errors in zink because those builtins can't be
used as input.

Fixes: e2220ee55e ("zink: filled quad emulation gs generation function")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
2023-05-15 11:04:41 +00:00
antonino
474d93719e zink: handle interface blocks in copy_vars
Fixes: edaf49160e ("zink: fix array copying in pv lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
2023-05-15 11:04:41 +00:00
antonino
a4113fd021 zink: don't replace non generated gs
Zink replaced the gs emulation shader when the primitive type changes,
however it didn't check whether the gs being replaced was generated.

Fixes: eedbf9046e ("zink: handle switching between primitives")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
2023-05-15 11:04:41 +00:00
Qiang Yu
d1dd36a74e radeonsi: be able to use aco compiler for mono ps
Need to set AMD_DEBUG=useaco environment variable.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:11 +00:00
Qiang Yu
288adae512 radeonsi: fixup sampler desc for tg4 in nir
For ACO which won't do this for us. But we still can't
remove the same code in llvm because non-uniform sampler
is keept as index in nir.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:11 +00:00
Qiang Yu
521cbcb588 ac/llvm,radeonsi: enable lower_array_layer_round_even
ACO need this to be done in nir. Remove the llvm round code
because both radv and radeonsi do this in nir for both aco
and llvm.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:11 +00:00
Qiang Yu
38e064b674 radeonsi: clamp shadow texture reference in nir for aco
This is ported from the LLVM ac_shader_abi->clamp_shadow_reference
code.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:11 +00:00
Qiang Yu
b5409131ef radeonsi: pass use_aco to ac_nir_lower_ps
For dual source blend code emition in aco.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:11 +00:00
Qiang Yu
7180b16afc radeonsi: adjust ps args for aco
aco need explicite args including PS arg compaction and
scratch_offset.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:11 +00:00
Qiang Yu
474ddeffe6 radeonsi: resolve aco scratch addr symbols
Used for scratch buffer operation and reg spill when aco.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:11 +00:00
Qiang Yu
7aac3508dc radeonsi: add symbols to si_shader_binary
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:11 +00:00
Qiang Yu
6a360e4a71 radeonsi: add initial aco compile code
Only for monolithic PS.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:11 +00:00
Qiang Yu
91c91bb972 radeonsi: lower non uniform texture access when aco
aco need all resource have been lowered to descriptor.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:11 +00:00
Qiang Yu
f859436b55 radeonsi: add has_non_uniform_tex_access shader info
Can be used to skip nir_lower_non_uniform_access pass.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
563bdcc7fc radeonsi: lower vector const to scalar at last for aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
e252d87816 radeonsi: lower some 64bit ops aco does not support
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
9bc1fb4c07 ac/llvm,radeonsi: lower nir_fpow for aco and llvm
aco does not implement fpow, need nir to lower it
first. llvm will do by itself in the same way, so
we always lower fpow in nir now.

Remove the llvm fpow implementation that has special
handling for the muliplication. It's not used any
more and does not match GLSL spec as fpow(0,0)=NaN
but here we get 0.

There's some pixel changes for gl-radeonsi-stoney:
  ror-default 2 (no tolerance), 0 (1% tol.)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
19a8626f86 ac/llvm,radeonsi: lower some pack/unpack ops not supported by aco
aco only support the split vertion of these instructions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
fb2d0fb4a2 ac/llvm,radeonsi: lower ineg in nir
aco does not implement it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
3fae161ff2 ac/llvm,radeonsi: lower txf offset in nir
aco will complain if txf has offset. Not if other
texture ops.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
f13f9044db ac/llvm,radeonsi: lower fsin/fcos in nir
ACO only support nir_fsin/cos_amd.

There's some pixel changes for gl-radeonsi-stoney trace.
Different pixels:
  furmark  61 (no tolerance), 0 (1% tol.)
  gimark   93867 (no tolerance), 888 (1% tol.)
  tessmark 39 (no tolerance), 0 (1% tol.)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
f9d54b1d36 ac/llvm,radeonsi: lower idiv in nir
aco does not implement these idiv ops.

nir_lower_idiv is for idiv ops <= 32bit and ported from
llvm amdgpu, so llvm do the same.

nir_lower_divmod64 is for 64bit idiv ops.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
5fa06828b4 tgsi_to_nir: call nir_lower_int64 when required
Use case: radeonsi will generate internal tgsi shader
with 64bit udiv instruction, and we want all 64bit udiv
to be lowered in nir by lower_int64_options.

For GLSL shaders, this is done in glsl to nir, so we do
the same for tgsi here.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
636f628206 radeonsi: remove ps vgpr index save when args init
They will be set by ac_get_fs_input_vgpr_cnt() later anyway.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
1eddf5934b radeonsi: support print raw shader binary
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
ff29502df2 radeonsi: support raw shader binary upload
Only monolithic shader.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
f3997a3ca7 radeonsi: add a raw shader binary type
It's the output of ACO compiler. To share the si_shader_binary
struct with ELF type:
  * add a type field to indicate RAW or ELF
  * rename elf_buffer/size to code_buffer/size

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
83a920dfb9 radeonsi: init spi ps input shader config when aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
f954aa1624 radeonsi: pack spi ps input fixup to a function
To be shared with ACO spi ps input construction.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
e752248b3b radeonsi: add shader info uses_sampleid
Used by ACO to set spi_ps_intput.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
14d2b12390 radeonsi: add shader info for frag coord and sample pos read
To construct spi_ps_input when ACO compilation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
326b027b25 radeonsi: add use_aco field for struct si_shader
We are going to use aco for monolithic ps first.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
ad33ff4de2 radeonsi: add aco debug option
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
Qiang Yu
5bc6c62486 meson: build radeonsi with aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
2023-05-15 02:01:10 +00:00
M Henning
be5b5fbe3d nv50: Fix return type of nv50_blit_is_array
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>
2023-05-13 19:36:24 +00:00
M Henning
504907a7d3 nvc0: Free blitter->vp
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>
2023-05-13 19:36:24 +00:00
M Henning
ae6ae84a75 nv50,nvc0: Free nir from blitter fp shader
Fixes: d11145e837 ("nv50,nvc0: Use nir in nv50_blitter_make_fp")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>
2023-05-13 19:36:24 +00:00
Marek Olšák
f98871608c ac/llvm: rewrite and unify how GLC, DLC, SLC are set
Use ACCESS_* flags in call sites instead of GLC/DLC/SLC.

ACCESS_* flags are extended to describe other aspects of memory instructions
like load/store/atomic/smem.

Then add a function that converts the access flags to GLC, DLC, SLC.

The new functions are also usable by ACO.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>
2023-05-12 21:45:44 +00:00
Felix DeGrood
82f6a477f3 intel: refactor INTEL_MEASURE pointer dumping
Refactor framebuffer to renderpass to mirror previous INTEL_MEASURE
changes.

We dump hashes/pointers for shaders and framebuffer/renderpass.
Reduce from 64bit to 32bit pointers. We don't benefit from the
extra precision and reduced output size is convenient.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
2023-05-12 21:15:09 +00:00
Alyssa Rosenzweig
ee6ddce636 ir3: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
b98b7f4d85 zink: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
d0d2292ac0 ntt: Use unified atomics
Nice deduplication of the NIR->TGSI enum translation.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
bd0a2b1608 gallivm: Use unified atomics
This is a huge win because gallivm duplicated the translations in a zillion
places.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Dmitry Rogozhkin
8fc5dd935f meson/vaon12: fix driver file name for mingw build
This fixes vaon12 driver file name to be consistent with libva
expectation - vaon12_drv_video.dll - without lib prefix.

Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22995>
2023-05-12 19:31:26 +00:00
Yiwei Zhang
aa57e8ef18 lvp: avoid accessing member of NULL ptr for global entries
Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22979>
2023-05-12 19:05:23 +00:00
Yiwei Zhang
5b31039033 pipe-loader: avoid undefined memcpy behavior
If either dest or src is an invalid or null pointer, the behavior is
undefined, even if count is zero.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22979>
2023-05-12 19:05:23 +00:00
Mike Blumenkrantz
d5cf6f7d2f zink: disable dynamic state exts if the previous ones aren't present
this would be weird if a driver did it

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22996>
2023-05-12 17:53:02 +00:00
Mike Blumenkrantz
6debee51f3 zink: disable have_EXT_vertex_input_dynamic_state without EDS2
this is disabled already in the draw paths but not the pipeline paths

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22996>
2023-05-12 17:53:02 +00:00
Mike Blumenkrantz
0f5a27ca8d zink: add back some anv qbo flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22987>
2023-05-12 09:10:04 -04:00