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radeonsi: lower non uniform texture access when aco

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aco need all resource have been lowered to descriptor.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
This commit is contained in:
Qiang Yu 2023-04-27 19:33:32 +08:00 • committed by Marge Bot
parent f859436b55
commit 91c91bb972
1 changed files with 8 additions and 0 deletions
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8
src/gallium/drivers/radeonsi/si_shader.c
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@ -2138,6 +2138,14 @@ struct nir_shader *si_get_nir_shader(struct si_shader *shader,
if (!sel->screen->info.has_image_opcodes)
NIR_PASS(progress, nir, ac_nir_lower_image_opcodes);
/* LLVM does not work well with this, so is handled in llvm backend waterfall. */
if (shader->use_aco && sel->info.has_non_uniform_tex_access) {
nir_lower_non_uniform_access_options options = {
.types = nir_lower_non_uniform_texture_access,
};
NIR_PASS(progress, nir, nir_lower_non_uniform_access, &options);
}
NIR_PASS(progress, nir, si_nir_lower_resource, shader, args);
bool is_last_vgt_stage =