Commit graph

186587 commits

Author SHA1 Message Date
Robert Mader
b2719a73c1 crocus: Support offset query for multi-planar planes
Multi-planar planes can be imported from VA-API or V4L2. In this case we
would currently report wrong values for `gbm_bo_get_offset()`.

This does not fix any know visible bug, as crocus hardware usually does
not support muliti-planar planes in the display engine - in which case
the wrong values would make Mutter glitch. Lets report correct values
regardless.

While on it, also use the helper function for counting planes.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28225>
2024-03-21 17:49:31 +00:00
duncan.hopkins
899fcaf237 zink: Avoid issues when kopper tries using XCB WSI on Apple.
On macOS builds the code is tryng to use X11 and XCB code paths for WSI functions and structures,
i.e. `VkXcbSurfaceCreateInfoKHR` and `vkCreateXcbSurfaceKHR()`.
The MoltenVK implementation only supports `VkMacOSSurfaceCreateInfoMVK` and `vkCreateMacOSSurfaceMVK()`.
To get these working correctly Metal diusplay surfaces need to be setup, which xquarts does not expose.

Until this situation is resolved correctly the `VK_STRUCTURE_TYPE_XCB_SURFACE_CREATE_INFO_KHR` code paths has been
changed to return `VK_INCOMPLETE`. This allows them to run without asserting and terminating the runtime.
This allows for non-display applicaitons, like `glxinfo`, to run without terminating.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28259>
2024-03-21 17:22:34 +00:00
duncan.hopkins
d644b64ff2 zink: removed MESA_PRIM_QUADS from the supported PIPE_CAP_SUPPORTED_PRIM_MODES.
Vulkan does not support quads, removal of this type forces quads to be converted
in `primconvert_init_draw()`.

In cases where `screen->have_triangle_fans` excludes MESA_PRIM_TRIANGLE_FAN,
`u_index_generator()` is accessing a NULL entry in 'generate_quads'
for converting MESA_PRIM_TRIANGLE_FAN to MESA_PRIM_QUADS.
Which seems like an odd conversion to do (might be why it is missing).

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28259>
2024-03-21 17:22:34 +00:00
duncan.hopkins
7e1e0c6824 zink: stopped the use of VkFormatProperties3 if the reported API is less than 1.3 or VK_KHR_format_feature_flags2 not present.
The MoltenVK (time of writing) only implements Vulkan 1.2 APIs and no `VK_KHR_format_feature_flags2` device extension.
This means VkFormatProperties3 is not supported, and is left blank when used in `populate_format_props()`.
If non-1.3 is detected then the same values are read from the `VkFormatProperties2` `props` location.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28259>
2024-03-21 17:22:34 +00:00
duncan.hopkins
d0015ebbab zink: use portability EXT on Apple.
Vulkan behaviour has changed to require VK_INSTANCE_CREATE_ENUMERATE_PORTABILITY_BIT_KHR
and VK_KHR_portability_enumeration to be used on layered Vulkan implementations.
These are enbaled on macOS/Apple as MoltenVK is the only implmentation (time of writing)
and newer version require this.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28259>
2024-03-21 17:22:34 +00:00
duncan.hopkins
32ac90d8c2 zink: Fixed header location and compiling issue with [[deprecated]] from newer MoltenVK versions.
From Vulkan 1.3.250 the MoltenVK include filenames changed.
Now include the newer 'MoltenVK/mvk_vulkan.h' instead of the older `MoltenVK/vk_mvk_moltenvk.h` headers.

From Vulkan 1.3.275 the MoltenVK include location changed.
The meson build options 'moltenvk-dir' now needs to point at the root of the Vulkan SDK install.
It will look for the presence of the older 'MoltenVK/include' loction and the newer 'macos/include' location.

Tested against Vulkan SDK versions: 1.3.250, 1.3.261, 1.3.268, 1.3.275.
Will not work compile with Vulkan 1.3.234 or earlier.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28259>
2024-03-21 17:22:34 +00:00
José Roberto de Souza
47bbd1c7ff intel/tools/error_decode: Parse HW context in Xe decoder
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27888>
2024-03-21 16:59:09 +00:00
José Roberto de Souza
ec3a41960b intel/tools/error_decode: Add function to print batch in Xe decoder
This will be useful to decode HW context in the next patch.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27888>
2024-03-21 16:59:09 +00:00
José Roberto de Souza
171eb89b75 intel/tools/error_decode: Fix parsing in Xe decoder
xe_topic can't be inside of the for loop otherwise it will be set to
TOPIC_INVALID at every iteration.

TOPIC_INVALID was added after it was reviewed by Lionel because CI
complained that xe_topic may be not initialized, turns out leaving it
not initialized was causing the xe_topic value to keep the value set
in the previous interation makeing the parser to work by luck.

Fixes: 90e38bbb3b ("intel/tools/error_decode: Parse Xe KMD error dump file")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27888>
2024-03-21 16:59:09 +00:00
Dylan Baker
477943cc9d meson: Allow building intel-clc for the host if it can be run
In what is probably the most common case  cross of compilation, x86_64
-> x86, it should be possible to build intel-clc for the host machine
and run it. Doing so simplifies the build by not needing to be able to
cross compile half of mesa, and should ease developer and distro strain
for building Intel drivers for x86.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28222>
2024-03-21 16:31:35 +00:00
Lionel Landwerlin
098136e52a anv: avoid partially compiled warning with GPL
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28318>
2024-03-21 16:09:54 +00:00
Vignesh Raman
3983ae89e9 Split debian-build-testing job
Split the build job from the shader-db tests so that the test
job can be rerun more reliably without hitting the timeout.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/9513
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27507>
2024-03-21 13:26:20 +00:00
Mike Blumenkrantz
ee13512a62 zink: clamp swapchain renderarea instead of asserting
in a sequence like:
* resize A
* clear
* resize B
* clear
* resize C
* clear

for a swapchain resource, the geometry for a given op after the resize
may desync for the op with which it was executed, but this is fine
since the underlying swapchain object will have to be re-created anyway

fixes #10827

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28214>
2024-03-21 13:05:04 +00:00
Mike Blumenkrantz
27f42a38aa zink: clamp present region size
it's illegal for these to exceed the size of the swapchain

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28214>
2024-03-21 13:05:04 +00:00
Mike Blumenkrantz
1670c40557 zink: defer present barrier to flush if a clear is pending
this otherwise submits the swapchain with the wrong layout

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28214>
2024-03-21 13:05:04 +00:00
Christian Gmeiner
7e686fa417 etnaviv: isa: Define a dontcare bit in atomic instructions
Looks like it is the same as for ALU instructions: skpHp

This simplifies the special atomic handling a lot. Seen on blob
running a simple opencl shader on GC3000.

__kernel void kern(
   __global int *a,
   __global int *b,
   __global int *result)
{
   atomic_add(result, a[0]);
}

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28272>
2024-03-21 12:24:35 +00:00
Iago Toral Quiroga
83f53be8c7 broadcom/ci: add skips for unsupported features
Currently 92% of our Vulkan CI tests hit "Not Supported" test
cases, which is ridiculously high. Add a bunch of skips, some
of which include very large categories of tests of features we
already know we don't support, so we stop wasting so much time
skipping tests.

With this, we can also increase the fraction of tests we execute
for vulkan significantly, while still keeping job run times
under control.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28264>
2024-03-21 11:47:50 +00:00
Eric Engestrom
795046a8d4 v3dv/ci: update expectations
A big chunk of the new flakes and timeouts are caused by enabling new
tests in f977e4d4f5 ("v3dv: Enable
EXT_swapchain_maintenance1").

I'm not quite sure what happened with
`dEQP-VK.wsi.wayland.swapchain.simulate_oom.*` but now at least half of
them are flaky on rpi4 (between Skip and Crash), so moving the whole
block to flakes. On rpi5 I haven't seen them flake yet so tentatively
removing them entirely, but there's a good chance the issue is common
and they'll have to be put into flakes on rpi5 at some point as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28316>
2024-03-21 11:20:18 +00:00
Samuel Pitoiset
4b065fe863 zink/ci: update CI lists
This seems to have been fixed quite recently.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28315>
2024-03-21 10:38:18 +01:00
Christian Gmeiner
e0ca29e7a3 isaspec: deocde: Remove generic functions from public interface
This will switch everyone to the isa specific functions.

Fixes the output of etnaviv's pre_instr_cb callback if
freedreno and etnaviv are build at the same time.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
3f2295d99b isaspec: decode: Add libisaspec
Create a static library that just contains isa_print(..). We
need to do this step to make lto happy.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
878fa2032e isaspec: deocde: Make isa_decode_field(..) private
Without this change the isa_decode_field(..) uses the wrong bitmask_t
type (freedreno: array with 2 elements, etnaviv: array with 4 elements)
and weird things happens.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
872f714e32 isaspec: deocde: Make isa_bitset arrays static
Without this commit etnaviv_isa_disasm(..) will call into
find_field(..) and use the bitsets are the one from freedreno.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
1196b82815 etnaviv: isa: Rework meson dependency for libetnaviv_decode
Any component that links against libetnaviv_decode should not need to
take care if the generated isa files exists.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
f396899983 freedreno/isa: Rework meson dependency for libir3decode
Any component that links against libir3decode should not need to
take care if the generated isa files exists.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
505ec13f87 isaspec: decode: Make isa_decode_bitset(..) private
Fixes lto issues later in the series.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
77872bec95 isaspec: decode: Add isa specific functions
In the end we want to only the specific functions and remove
the generic ones from the public interface.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
16e8a3548f isaspec: deocde: Hide all the internals ISA details
There are no users of these defines, structs and functions
outside of the generated isa.c file. I left the empty header
as it will be used in later commits.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
08e899852b isaspec: Remove not used isa_decode_hook
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:17 +00:00
Marek Olšák
651191801a gallium: increase the size of pipe_box y, height fields to allow bigger textures
and reorder the fields to pack them better

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27953>
2024-03-21 03:33:39 +00:00
Marek Olšák
bfdbfd6ade gallium: use u_box_3d to initialize pipe_box instead of non-designated initializers
This is the original utility for initializing pipe_box.
It prevents breakage when pipe_box fields are reordered.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27953>
2024-03-21 03:33:39 +00:00
Karol Herbst
dc57c6b59e rusticl/util: make create_pipe_box indepentend of pipe_box's field types
This way one can freely change the types of fields inside pipe_box without
running into compilation errors here.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27953>
2024-03-21 03:33:39 +00:00
Patrick Lerda
0fd907fc7b ac/llvm,radeonsi: fix memory leaks triggered by ac_nir_translate() errors
For instance, this issue is triggered with
"piglit/bin/glslparsertest tests/spec/arb_bindless_texture/compiler/images/arith-bound-image.frag pass 3.30 GL_ARB_bindless_texture GL_ARB_shader_image_load_store":
Direct leak of 176 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbe9a7 in calloc (/usr/lib64/libasan.so.6+0xb19a7)
    #1 0x7f84ba7e0801 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4391
    #2 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
    #3 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
    #4 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #5 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #6 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #7 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #8 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

Direct leak of 136 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbff57 in operator new(unsigned long) (/usr/lib64/libasan.so.6+0xb2f57)
    #1 0x7f84b1a5f749 in LLVMCreateBuilderInContext (/usr/local/lib64/libLLVM-17.so+0xc84749)
    #2 0x7f84ba7817b0 in ac_llvm_context_init ../src/amd/llvm/ac_llvm_build.c:54
    #3 0x7f84ba542b7a in si_llvm_context_init ../src/gallium/drivers/radeonsi/si_shader_llvm.c:120
    #4 0x7f84ba542b7a in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:832
    #5 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #6 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #7 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #8 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #9 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

Indirect leak of 176 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
    #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
    #2 0x7f84b81b9fee in rzalloc_size ../src/util/ralloc.c:152
    #3 0x7f84b81b9fee in rzalloc_array_size ../src/util/ralloc.c:232
    #4 0x7f84b81b05c7 in _mesa_hash_table_init ../src/util/hash_table.c:163
    #5 0x7f84b81b05c7 in _mesa_hash_table_create ../src/util/hash_table.c:186
    #6 0x7f84ba7e06ae in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4381
    #7 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
    #8 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
    #9 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #10 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #11 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #12 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #13 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

Indirect leak of 176 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
    #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
    #2 0x7f84b81b9fee in rzalloc_size ../src/util/ralloc.c:152
    #3 0x7f84b81b9fee in rzalloc_array_size ../src/util/ralloc.c:232
    #4 0x7f84b81b05c7 in _mesa_hash_table_init ../src/util/hash_table.c:163
    #5 0x7f84b81b05c7 in _mesa_hash_table_create ../src/util/hash_table.c:186
    #6 0x7f84ba7e06e4 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4382
    #7 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
    #8 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
    #9 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #10 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #11 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #12 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #13 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

Indirect leak of 128 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
    #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
    #2 0x7f84b81b046c in _mesa_hash_table_create ../src/util/hash_table.c:182
    #3 0x7f84ba7e06e4 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4382
    #4 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
    #5 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
    #6 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #7 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #8 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #9 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #10 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

Indirect leak of 128 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
    #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
    #2 0x7f84b81b046c in _mesa_hash_table_create ../src/util/hash_table.c:182
    #3 0x7f84ba7e06ae in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4381
    #4 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
    #5 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
    #6 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #7 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #8 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #9 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #10 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

SUMMARY: AddressSanitizer: 920 byte(s) leaked in 6 allocation(s).

Fixes: d92d35c9db ("ac/llvm: add a return value to ac_nir_translate")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28099>
2024-03-21 00:51:19 +00:00
Ian Romanick
3556dbb97f intel/brw/xe2: Correctly disassemble RT write subtypes
The encoding changed when SIMD32 was added.

Part of Wa_14011334914.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Francisco Jerez
871805215a iris/xe2+: Disable coherent framebuffer fetch.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Francisco Jerez
c4325f426c intel/brw/xe2+: Setup PS thread payload registers required for ALU-based pixel interpolation.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Francisco Jerez
6427f16074 intel/brw/gfx12: Setup PS thread payload registers required for ALU-based pixel interpolation.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Rohan Garg
2df6d208c8 intel/brw: Adjust src1 length bits for xe2+
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Rohan Garg
83f2bdc116 intel/brw: Set the right cache control bits for xe2
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Rohan Garg
adb853ed10 intel/brw: Update written size depending on the LSC message
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Rohan Garg
48376ac3b8 intel/brw: Cleanup send generation
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Rohan Garg
65f66974a5 intel/brw: Use the dimensions supplied in the instruction
Rework:
 * Francisco Jerez: Rebase on 07b9bfacc7 ("intel/compiler: Move
   logical-send lowering to a separate file")

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Francisco Jerez
644a0ede1e intel/blorp/xe2+: Don't use replicated-data clears.
They've been removed from the hardware.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Francisco Jerez
af8b9af700 intel/brw/xe2+: Allow dual-source blending in SIMD16 mode.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Francisco Jerez
762ec3fd59 intel/brw/xe2+: Allow FS stencil output in SIMD16 dispatch mode.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Francisco Jerez
efc0601ddf intel/brw/xe2+: Double allowed SIMD width of FB write SEND messages.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Francisco Jerez
d96bfb160f intel/brw/xe2+: Update encoding of FB write extended descriptor.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Francisco Jerez
189422de1b intel/brw/xe2+: Update encoding of FB write descriptor message control.
Ref: bspec: 65209, 63908
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Francisco Jerez
7b0fbc22dd intel/brw/xe2: Render target reads have been removed from the hardware.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
2024-03-20 15:46:44 -07:00
Paulo Zanoni
6ec1e322f0 anv: don't leak device->vma_samplers
The vma_samplers vma heap is initialized unconditionally. Don't use
device->physical->indirect_descriptors as a condition on whether to
free it or not.

From my TGL machine:

==373617== 32 bytes in 1 blocks are definitely lost in loss record 1 of 1
==373617==    at 0x48459F3: calloc (in /usr/libexec/valgrind/vgpreload_memcheck-amd64-linux.so)
==373617==    by 0x6926DC0: util_vma_heap_free (vma.c:339)
==373617==    by 0x6925ED3: util_vma_heap_init (vma.c:53)
==373617==    by 0x5334EDA: anv_CreateDevice (anv_device.c:3404)
==373617==    by 0x685593A: vk_tramp_CreateDevice (vk_dispatch_trampolines.c:78)
==373617==    by 0x48A6D56: terminator_CreateDevice (loader.c:5833)
==373617==    by 0x9C2293F: vulkan_layer_chassis::CreateDevice(VkPhysicalDevice_T*, VkDeviceCreateInfo const*, VkAllocationCallbacks const*, VkDevice_T**) (chassis.cpp:497)
==373617==    by 0x48B0690: loader_create_device_chain (loader.c:4937)
==373617==    by 0x48B1327: loader_layer_create_device (loader.c:4317)
==373617==    by 0x48B8D79: vkCreateDevice (trampoline.c:1004)
==373617==    by 0x10CC7A: MyApp::MyApp(int, bool) (sparse.cpp:608)
==373617==    by 0x1201E8: main (sparse.cpp:6025)

Fixes: 7c76125db2 ("anv: use 2 different buffers for surfaces/samplers in descriptor sets")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28303>
2024-03-20 21:55:55 +00:00