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intel/brw: Set the right cache control bits for xe2

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Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
This commit is contained in:
Rohan Garg 2022-07-28 18:48:25 +02:00 • committed by Jordan Justen
parent adb853ed10
commit 83f2bdc116
1 changed files with 3 additions and 2 deletions
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5
src/intel/compiler/brw_eu.h
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@ -1168,7 +1168,8 @@ lsc_msg_desc_wcmask(UNUSED const struct intel_device_info *devinfo,
SET_BITS(addr_sz, 8, 7) |
SET_BITS(data_sz, 11, 9) |
SET_BITS(transpose, 15, 15) |
SET_BITS(cache_ctrl, 19, 17) |
(devinfo->ver >= 20 ? SET_BITS(cache_ctrl, 19, 16) :
SET_BITS(cache_ctrl, 19, 17)) |
SET_BITS(dest_length, 24, 20) |
SET_BITS(src0_length, 28, 25) |
SET_BITS(addr_type, 30, 29);
@ -1249,7 +1250,7 @@ lsc_msg_desc_cache_ctrl(UNUSED const struct intel_device_info *devinfo,
uint32_t desc)
{
assert(devinfo->has_lsc);
return GET_BITS(desc, 19, 17);
return devinfo->ver >= 20 ? GET_BITS(desc, 19, 16) : GET_BITS(desc, 19, 17);
}
static inline unsigned