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intel/brw: Adjust src1 length bits for xe2+

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Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28306>
This commit is contained in:
Rohan Garg 2022-08-02 17:31:50 +02:00 • committed by Jordan Justen
parent 83f2bdc116
commit 2df6d208c8
1 changed files with 6 additions and 2 deletions
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8
src/intel/compiler/brw_eu.h
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@ -305,14 +305,18 @@ brw_message_ex_desc(const struct intel_device_info *devinfo,
unsigned ex_msg_length)
{
assert(ex_msg_length % reg_unit(devinfo) == 0);
return SET_BITS(ex_msg_length / reg_unit(devinfo), 9, 6);
return devinfo->ver >= 20 ?
SET_BITS(ex_msg_length / reg_unit(devinfo), 10, 6) :
SET_BITS(ex_msg_length / reg_unit(devinfo), 9, 6);
}
static inline unsigned
brw_message_ex_desc_ex_mlen(const struct intel_device_info *devinfo,
uint32_t ex_desc)
{
return GET_BITS(ex_desc, 9, 6) * reg_unit(devinfo);
return devinfo->ver >= 20 ?
GET_BITS(ex_desc, 10, 6) * reg_unit(devinfo) :
GET_BITS(ex_desc, 9, 6) * reg_unit(devinfo);
}
static inline uint32_t