Mesa builds using -Dperfetto=true generate a pps-producer binary.
Include it in the artifacts for use in runtime performance tracing
tests.
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38517>
Enable Perfetto tracing support in Mesa's x86_64/arm64 builds for Linux
and Android. This enables GPU performance counter collection via pps and
sets up the environment for runtime GL tests with support for CPU, GPU
and system-wide tracing. Information captured by Perfetto will provide
driver developers insight into the test environment and help identify
factors affecting performance.
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38517>
This should be ignored on non-compute stages but AGX changes 3D shaders
to compute without setting the workgroup size and blows up if it claims
variable workgroups. The safest thing is to only set it from
spirv_to_nir for stages that actually have workgroups.
Fixes: 6d9f563960 ("spirv: Assume variable workgroup size unless it's set")
LoLed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38555>
This is strictly a GL thing. iris can manage it in its own program keys
without polluting the compiler with stuff nobody else cares about.
We can also drop a lot of padding that was introduced in commit
a18835a9ca which doesn't appear to be
necessary.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38556>
We're storing iris keys here, not brw keys. This worked because brw
keys are larger so you could fit any iris key in the memory.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38556>
The versioning scheme changed in v45.0 (the previous version was
3.48.0). As such, this version check would wrongly accept e.g. 48.0.
Fixes: e9341568fa ("meson: require sysprof-capture-4 >= 4.49.0")
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38557>
We don't have to enter the lower-IO-to-temps block for TCS at all.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38470>
Previously legacy_gs_info calculated based on
gs_info->legacy_gs_info.esgs_itemsize which is calculated based on gs
input varyings.
However, when using ESO vs/tes can have outputs not read by gs, which
leads to underestimating LDS usage.
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38514>
One might think that the `64B` bit might be affecting just the
memory size, but that's not the case as it affects the register
count too. Setting `64B` with `CNT` of `1` actually copies 2
registers, and not 1.
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38535>
This makes it possible for these to be used in static_asserts or if
we want to get a register offset (gen agnostic) and have it be
marked as constexpr. E.g.
```
constexpr uint32_t src_reg = __TPL1_A2D_SRC_TEXTURE_BASE<CHIP>({}).reg;
```
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38549>
Attempting to separate things out by gen is a bit arbitrary. And gets
increasingly awkward as we introduce gen8 support, which builds on gen7
but changes some a6xx values.
Just move it all into a single 'props' struct.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
These two regs only exist in a6xx. And only need a static value. So
move them to raw_magic_regs and drop the fd_dev_info field and
corresponding driver code.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
Sadly this probably won't change anything in terms of perf as the CCS
engine has a bunch of other restrictions.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 243c01c703 ("anv/iris: implement Wa_18040903259")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38484>
When there are no color outputs in the rendering state, but color write
enable/write aren't masked out (which seems legal with
VK_EXT_dynamic_rendering_unused_attachments), the driver must emit
CB_DISABLE to disable CB rendering completely.
Otherwise, if there is also a depth/stencil attachment in the rendering
state, CB0 is always set to 32_R for RB+. That means, the pixel shader
would still export fragments but to the previously bound color
attachment.
VKCTS is missing coverage.
Fixes: 4580293ab2 ("radv: implement RB+ depth-only rendering for better perf")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14319
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38509>
The old one was abandoned without so much as a README note.
This will also allow using newer releases than 47; the current one being
53, but this MR doesn't address that, as it aims to be a simple no-op
change.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38525>
Previously, we update the sfb dst slot upon vn_SignalSemaphore so that
vn_GetSemaphoreCounterValue can poll just the feedback slot itself.
However, that can race with pending sfb cmds that are going to update
the slot value, ending up with stuck sync progression.
This change fixes it by disallowing vn_SignalSemaphore to touch the sfb
dst slot. To ensure counter query being monotonic, vn_GetSemaphoreCounterValue
now takes the greater of signaled counter and the sfb counter read.
Test with dEQP-VK.synchronization* group:
- w/o this: stuck shows up within 2 min with 8 parallel deqp runs
- with this: no stuck for multiple full runs of the same
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14304
Fixes: 5c7e60362c ("venus: enable timeline semaphore feedback")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38516>
