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freedreno: Flatten fd_dev_info props

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Attempting to separate things out by gen is a bit arbitrary.  And gets
increasingly awkward as we introduce gen8 support, which builds on gen7
but changes some a6xx values.

Just move it all into a single 'props' struct.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
This commit is contained in:
Rob Clark 2025-11-18 15:39:09 -08:00 • committed by Marge Bot
parent 062e90f19b
commit 43dd11ca6a
41 changed files with 367 additions and 363 deletions
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4
src/freedreno/common/fd6_pack.h
View file

@ -125,9 +125,9 @@ public:
*
* set_bin_size<CHIP>(crb, gmem, {
* .render_mode = RENDERING_PASS,
* .force_lrz_write_dis = !screen->info->a6xx.has_lrz_feedback,
* .force_lrz_write_dis = !screen->info->props.has_lrz_feedback,
* .buffers_location = BUFFERS_IN_GMEM,
* .lrz_feedback_zmode_mask = screen->info->a6xx.has_lrz_feedback
* .lrz_feedback_zmode_mask = screen->info->props.has_lrz_feedback
* ? LRZ_FEEDBACK_EARLY_Z_LATE_Z
* : LRZ_FEEDBACK_NONE,
* });

11
src/freedreno/common/freedreno_dev_info.h
View file

@ -70,6 +70,9 @@ struct fd_dev_info {
};
struct {
/*
* A6XX / gen6
*/
uint32_t reg_size_vec4;
/* The size (in instrlen units (128 bytes)) of instruction cache where
@ -263,9 +266,11 @@ struct fd_dev_info {
/* True if PC_DGEN_SO_CNTL is present. */
bool has_pc_dgen_so_cntl;
} a6xx;
struct {
/*
* A7XX / gen7
*/
/* stsc may need to be done twice for the same range to workaround
* _something_, observed in blob's disassembly.
*/
@ -382,7 +387,7 @@ struct fd_dev_info {
* driver.
*/
bool has_hw_bin_scaling;
} a7xx;
} props;
};
struct fd_dev_id {

13
src/freedreno/common/freedreno_devices.py
View file

@ -166,16 +166,15 @@ class A6xxGPUInfo(GPUInfo):
self.num_ccu = num_ccu
self.a6xx = Struct()
self.a7xx = Struct()
self.props = Struct()
self.a6xx.magic = Struct()
self.props.magic = Struct()
for name, val in magic_regs.items():
setattr(self.a6xx.magic, name, val)
setattr(self.props.magic, name, val)
if raw_magic_regs:
self.a6xx.magic_raw = [[int(r[0]), r[1]] for r in raw_magic_regs]
self.props.magic_raw = [[int(r[0]), r[1]] for r in raw_magic_regs]
templates = template if isinstance(template, list) else [template]
for template in templates:
@ -311,12 +310,12 @@ class A6XXProps(dict):
A6XXProps.unique_props[(name, gen)] = val
def apply_props(self, gpu_info):
self.apply_gen_props("a6xx", gpu_info)
self.apply_gen_props("props", gpu_info)
class A7XXProps(A6XXProps):
def apply_props(self, gpu_info):
self.apply_gen_props("a7xx", gpu_info)
self.apply_gen_props("props", gpu_info)
# Props could be modified with env var:

16
src/freedreno/common/freedreno_ubwc.h
View file

@ -33,11 +33,11 @@ fd6_ubwc_compat_mode(const struct fd_dev_info *info, enum pipe_format format)
switch (format) {
case PIPE_FORMAT_R8G8_UNORM:
case PIPE_FORMAT_R8G8_SRGB:
return info->a7xx.ubwc_unorm_snorm_int_compatible ?
return info->props.ubwc_unorm_snorm_int_compatible ?
FD6_UBWC_R8G8_INT : FD6_UBWC_R8G8_UNORM;
case PIPE_FORMAT_R8G8_SNORM:
return info->a7xx.ubwc_unorm_snorm_int_compatible ?
return info->props.ubwc_unorm_snorm_int_compatible ?
FD6_UBWC_R8G8_INT : FD6_UBWC_UNKNOWN_COMPAT;
case PIPE_FORMAT_R8G8_UINT:
@ -46,11 +46,11 @@ fd6_ubwc_compat_mode(const struct fd_dev_info *info, enum pipe_format format)
case PIPE_FORMAT_R8G8B8A8_UNORM:
case PIPE_FORMAT_R8G8B8A8_SRGB:
return info->a7xx.ubwc_unorm_snorm_int_compatible ?
return info->props.ubwc_unorm_snorm_int_compatible ?
FD6_UBWC_R8G8B8A8_INT : FD6_UBWC_R8G8B8A8_UNORM;
case PIPE_FORMAT_R8G8B8A8_SNORM:
return info->a7xx.ubwc_unorm_snorm_int_compatible ?
return info->props.ubwc_unorm_snorm_int_compatible ?
FD6_UBWC_R8G8B8A8_INT : FD6_UBWC_UNKNOWN_COMPAT;
case PIPE_FORMAT_R8G8B8A8_UINT:
@ -58,11 +58,11 @@ fd6_ubwc_compat_mode(const struct fd_dev_info *info, enum pipe_format format)
return FD6_UBWC_R8G8B8A8_INT;
case PIPE_FORMAT_R16G16_UNORM:
return info->a7xx.ubwc_unorm_snorm_int_compatible ?
return info->props.ubwc_unorm_snorm_int_compatible ?
FD6_UBWC_R16G16_INT : FD6_UBWC_R16G16_UNORM;
case PIPE_FORMAT_R16G16_SNORM:
return info->a7xx.ubwc_unorm_snorm_int_compatible ?
return info->props.ubwc_unorm_snorm_int_compatible ?
FD6_UBWC_R16G16_INT : FD6_UBWC_UNKNOWN_COMPAT;
case PIPE_FORMAT_R16G16_UINT:
@ -70,11 +70,11 @@ fd6_ubwc_compat_mode(const struct fd_dev_info *info, enum pipe_format format)
return FD6_UBWC_R16G16_INT;
case PIPE_FORMAT_R16G16B16A16_UNORM:
return info->a7xx.ubwc_unorm_snorm_int_compatible ?
return info->props.ubwc_unorm_snorm_int_compatible ?
FD6_UBWC_R16G16B16A16_INT : FD6_UBWC_R16G16B16A16_UNORM;
case PIPE_FORMAT_R16G16B16A16_SNORM:
return info->a7xx.ubwc_unorm_snorm_int_compatible ?
return info->props.ubwc_unorm_snorm_int_compatible ?
FD6_UBWC_R16G16B16A16_INT : FD6_UBWC_UNKNOWN_COMPAT;
case PIPE_FORMAT_R16G16B16A16_UINT:

12
src/freedreno/computerator/a6xx.cc
View file

@ -113,13 +113,13 @@ template<chip CHIP>
static void
cs_restore_emit(fd_cs &cs, struct a6xx_backend *a6xx_backend)
{
fd_ncrb<CHIP> ncrb(cs, 2 + ARRAY_SIZE(a6xx_backend->info->a6xx.magic_raw));
fd_ncrb<CHIP> ncrb(cs, 2 + ARRAY_SIZE(a6xx_backend->info->props.magic_raw));
ncrb.add(A6XX_SP_PERFCTR_SHADER_MASK(.cs = true));
ncrb.add(A6XX_SP_NC_MODE_CNTL_2());
for (size_t i = 0; i < ARRAY_SIZE(a6xx_backend->info->a6xx.magic_raw); i++) {
auto magic_reg = a6xx_backend->info->a6xx.magic_raw[i];
for (size_t i = 0; i < ARRAY_SIZE(a6xx_backend->info->props.magic_raw); i++) {
auto magic_reg = a6xx_backend->info->props.magic_raw[i];
if (!magic_reg.reg)
break;
@ -191,7 +191,7 @@ cs_program_emit_regs(fd_cs &cs, struct kernel *kernel)
(v->constlen > 128 ? CONSTLEN_192 : CONSTLEN_128));
crb.add(A6XX_SP_CS_CNTL_1(.shared_size = shared_size, .constantrammode = mode));
if (CHIP == A6XX && a6xx_backend->info->a6xx.has_lpac) {
if (CHIP == A6XX && a6xx_backend->info->props.has_lpac) {
crb.add(HLSQ_CS_CTRL_REG1(CHIP, .shared_size = 1, .constantrammode = mode));
}
@ -226,7 +226,7 @@ cs_program_emit_regs(fd_cs &cs, struct kernel *kernel)
));
}
if (CHIP == A7XX || a6xx_backend->info->a6xx.has_lpac) {
if (CHIP == A7XX || a6xx_backend->info->props.has_lpac) {
crb.add(A6XX_SP_CS_WIE_CNTL_0(
.wgidconstid = work_group_id,
.wgsizeconstid = INVALID_REG,
@ -283,7 +283,7 @@ cs_program_emit(fd_cs &cs, struct kernel *kernel)
cs_program_emit_regs<CHIP>(cs, kernel);
uint32_t shader_preload_size =
MIN2(v->instrlen, a6xx_backend->info->a6xx.instr_cache_size);
MIN2(v->instrlen, a6xx_backend->info->props.instr_cache_size);
fd_pkt7(cs, CP_LOAD_STATE6_FRAG, 3)
.add(CP_LOAD_STATE6_0(

2
src/freedreno/decode/crashdec.h
View file

@ -44,7 +44,7 @@ have_rem_info(void)
static inline bool
has_a7xx_gen3_control_regs(void)
{
return options.info->a7xx.new_control_regs;
return options.info->props.new_control_regs;
}
static inline bool

2
src/freedreno/fdl/fd6_format_table.c
View file

@ -432,7 +432,7 @@ bool
fd6_texture_format_supported(const struct fd_dev_info *info, enum pipe_format format,
enum a6xx_tile_mode tile_mode, bool is_mutable)
{
if (info->a6xx.is_a702) {
if (info->props.is_a702) {
/* BPTC is removed */
switch (format) {
case PIPE_FORMAT_BPTC_RGBA_UNORM:

2
src/freedreno/fdl/fd6_layout.c
View file

@ -168,7 +168,7 @@ fdl6_layout_image(struct fdl_layout *layout, const struct fd_dev_info *info,
if (util_format_is_depth_or_stencil(params->format))
layout->tile_all = true;
if (layout->ubwc && !info->a6xx.has_ubwc_linear_mipmap_fallback)
if (layout->ubwc && !info->props.has_ubwc_linear_mipmap_fallback)
layout->tile_all = true;
/* in layer_first layout, the level (slice) contains just one

6
src/freedreno/fdl/freedreno_lrz_layout.h
View file

@ -138,7 +138,7 @@ fdl6_lrz_layout_init(struct fdl_lrz_layout *lrz_layout,
layout->width0 + extra_width, layout->height0 + extra_height,
layout->nr_samples, array_layers);
if (!dev_info->a6xx.enable_lrz_fast_clear) {
if (!dev_info->props.enable_lrz_fast_clear) {
lrz_layout->lrz_fc_size = 0;
}
@ -146,8 +146,8 @@ fdl6_lrz_layout_init(struct fdl_lrz_layout *lrz_layout,
uint32_t lrz_size = lrz_layout->lrz_buffer_size *
(dev_info->chip >= 7 ? 2 : 1);
if (dev_info->a6xx.enable_lrz_fast_clear ||
dev_info->a6xx.has_lrz_dir_tracking) {
if (dev_info->props.enable_lrz_fast_clear ||
dev_info->props.has_lrz_dir_tracking) {
lrz_layout->lrz_fc_offset =
lrz_layout->lrz_offset + lrz_size;
lrz_size += sizeof(fd_lrzfc_layout<CHIP>);

54
src/freedreno/ir3/ir3_compiler.c
View file

@ -210,7 +210,7 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
*/
compiler->max_const_compute = compiler->gen >= 7 ? 512 : 256;
if (dev_info->a6xx.is_a702) {
if (dev_info->props.is_a702) {
/* No GS/tess, 128 per stage otherwise: */
compiler->max_const_compute = 128;
compiler->max_const_pipeline = 256;
@ -224,15 +224,15 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
compiler->has_preamble = true;
compiler->tess_use_shared = dev_info->a6xx.tess_use_shared;
compiler->tess_use_shared = dev_info->props.tess_use_shared;
compiler->has_getfiberid = dev_info->a6xx.has_getfiberid;
compiler->mov_half_shared_quirk = dev_info->a6xx.mov_half_shared_quirk;
compiler->has_movs = dev_info->a6xx.has_movs;
compiler->has_getfiberid = dev_info->props.has_getfiberid;
compiler->mov_half_shared_quirk = dev_info->props.mov_half_shared_quirk;
compiler->has_movs = dev_info->props.has_movs;
compiler->has_dp2acc = dev_info->a6xx.has_dp2acc;
compiler->has_dp4acc = dev_info->a6xx.has_dp4acc;
compiler->has_compliant_dp4acc = dev_info->a7xx.has_compliant_dp4acc;
compiler->has_dp2acc = dev_info->props.has_dp2acc;
compiler->has_dp4acc = dev_info->props.has_dp4acc;
compiler->has_compliant_dp4acc = dev_info->props.has_compliant_dp4acc;
if (compiler->gen == 6 && options->shared_push_consts) {
compiler->shared_consts_base_offset = 504;
@ -244,29 +244,29 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
compiler->geom_shared_consts_size_quirk = 0;
}
compiler->has_fs_tex_prefetch = dev_info->a6xx.has_fs_tex_prefetch;
compiler->stsc_duplication_quirk = dev_info->a7xx.stsc_duplication_quirk;
compiler->load_shader_consts_via_preamble = dev_info->a7xx.load_shader_consts_via_preamble;
compiler->load_inline_uniforms_via_preamble_ldgk = dev_info->a7xx.load_inline_uniforms_via_preamble_ldgk;
compiler->has_fs_tex_prefetch = dev_info->props.has_fs_tex_prefetch;
compiler->stsc_duplication_quirk = dev_info->props.stsc_duplication_quirk;
compiler->load_shader_consts_via_preamble = dev_info->props.load_shader_consts_via_preamble;
compiler->load_inline_uniforms_via_preamble_ldgk = dev_info->props.load_inline_uniforms_via_preamble_ldgk;
compiler->num_predicates = 4;
compiler->bitops_can_write_predicates = true;
compiler->has_branch_and_or = true;
compiler->has_predication = true;
compiler->predtf_nop_quirk = dev_info->a6xx.predtf_nop_quirk;
compiler->prede_nop_quirk = dev_info->a6xx.prede_nop_quirk;
compiler->has_scalar_alu = dev_info->a6xx.has_scalar_alu;
compiler->has_scalar_predicates = dev_info->a6xx.has_scalar_predicates;
compiler->has_isam_v = dev_info->a6xx.has_isam_v;
compiler->has_ssbo_imm_offsets = dev_info->a6xx.has_ssbo_imm_offsets;
compiler->fs_must_have_non_zero_constlen_quirk = dev_info->a7xx.fs_must_have_non_zero_constlen_quirk;
compiler->has_early_preamble = dev_info->a6xx.has_early_preamble;
compiler->predtf_nop_quirk = dev_info->props.predtf_nop_quirk;
compiler->prede_nop_quirk = dev_info->props.prede_nop_quirk;
compiler->has_scalar_alu = dev_info->props.has_scalar_alu;
compiler->has_scalar_predicates = dev_info->props.has_scalar_predicates;
compiler->has_isam_v = dev_info->props.has_isam_v;
compiler->has_ssbo_imm_offsets = dev_info->props.has_ssbo_imm_offsets;
compiler->fs_must_have_non_zero_constlen_quirk = dev_info->props.fs_must_have_non_zero_constlen_quirk;
compiler->has_early_preamble = dev_info->props.has_early_preamble;
compiler->has_rpt_bary_f = true;
compiler->has_shfl = true;
compiler->reading_shading_rate_requires_smask_quirk =
dev_info->a7xx.reading_shading_rate_requires_smask_quirk;
compiler->has_alias_rt = dev_info->a7xx.has_alias_rt;
dev_info->props.reading_shading_rate_requires_smask_quirk;
compiler->has_alias_rt = dev_info->props.has_alias_rt;
compiler->mergedregs = true;
compiler->has_sel_b_fneg = dev_info->a6xx.has_sel_b_fneg;
compiler->has_sel_b_fneg = dev_info->props.has_sel_b_fneg;
if (compiler->gen >= 7) {
compiler->has_alias_tex = true;
@ -307,7 +307,7 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
compiler->has_isam_ssbo = compiler->gen >= 6;
if (compiler->gen >= 6) {
compiler->reg_size_vec4 = dev_info->a6xx.reg_size_vec4;
compiler->reg_size_vec4 = dev_info->props.reg_size_vec4;
} else if (compiler->gen >= 4) {
/* On a4xx-a5xx, using r24.x and above requires using the smallest
* threadsize.
@ -351,21 +351,21 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
/* Set up nir shader compiler options, using device-specific overrides of our base settings. */
compiler->nir_options = ir3_base_options;
compiler->nir_options.has_iadd3 = dev_info->a6xx.has_sad;
compiler->nir_options.has_iadd3 = dev_info->props.has_sad;
if (compiler->gen >= 6) {
compiler->nir_options.force_indirect_unrolling = nir_var_all,
compiler->nir_options.lower_device_index_to_zero = true;
compiler->nir_options.instance_id_includes_base_index = true;
if (dev_info->a6xx.has_dp2acc || dev_info->a6xx.has_dp4acc) {
if (dev_info->props.has_dp2acc || dev_info->props.has_dp4acc) {
compiler->nir_options.has_udot_4x8 =
compiler->nir_options.has_udot_4x8_sat = true;
compiler->nir_options.has_sudot_4x8 =
compiler->nir_options.has_sudot_4x8_sat = true;
}
if (dev_info->a6xx.has_dp4acc && dev_info->a7xx.has_compliant_dp4acc) {
if (dev_info->props.has_dp4acc && dev_info->props.has_compliant_dp4acc) {
compiler->nir_options.has_sdot_4x8 =
compiler->nir_options.has_sdot_4x8_sat = true;
}

4
src/freedreno/vulkan/tu_autotune.cc
View file

@ -670,7 +670,7 @@ tu_autotune_begin_renderpass(struct tu_cmd_buffer *cmd,
&autotune_result->bo);
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNTER_CNTL(.copy = true));
if (cmd->device->physical_device->info->a7xx.has_event_write_sample_count) {
if (cmd->device->physical_device->info->props.has_event_write_sample_count) {
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE7, 3);
tu_cs_emit(cs, CP_EVENT_WRITE7_0(.event = ZPASS_DONE,
.write_sample_count = true).value);
@ -714,7 +714,7 @@ void tu_autotune_end_renderpass(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNTER_CNTL(.copy = true));
if (cmd->device->physical_device->info->a7xx.has_event_write_sample_count) {
if (cmd->device->physical_device->info->props.has_event_write_sample_count) {
/* If the renderpass contains ZPASS_DONE events we emit a fake ZPASS_DONE
* event here, composing a pair of these events that firmware handles without
* issue. This first event writes into the samples_end field and the second

22
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -557,30 +557,30 @@ r2d_teardown(struct tu_cmd_buffer *cmd,
static void
r2d_run(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
if (cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL_blit !=
cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL) {
if (cmd->device->physical_device->info->props.magic.RB_DBG_ECO_CNTL_blit !=
cmd->device->physical_device->info->props.magic.RB_DBG_ECO_CNTL) {
/* This a non-context register, so we have to WFI before changing. */
tu_cs_emit_wfi(cs);
tu_cs_emit_write_reg(
cs, REG_A6XX_RB_DBG_ECO_CNTL,
cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL_blit);
cmd->device->physical_device->info->props.magic.RB_DBG_ECO_CNTL_blit);
}
/* TODO: try to track when there has been a draw without any intervening
* WFI or CP_EVENT_WRITE and only WFI then.
*/
if (cmd->device->physical_device->info->a6xx.blit_wfi_quirk)
if (cmd->device->physical_device->info->props.blit_wfi_quirk)
tu_cs_emit_wfi(cs);
tu_cs_emit_pkt7(cs, CP_BLIT, 1);
tu_cs_emit(cs, CP_BLIT_0_OP(BLIT_OP_SCALE));
if (cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL_blit !=
cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL) {
if (cmd->device->physical_device->info->props.magic.RB_DBG_ECO_CNTL_blit !=
cmd->device->physical_device->info->props.magic.RB_DBG_ECO_CNTL) {
tu_cs_emit_wfi(cs);
tu_cs_emit_write_reg(
cs, REG_A6XX_RB_DBG_ECO_CNTL,
cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL);
cmd->device->physical_device->info->props.magic.RB_DBG_ECO_CNTL);
}
}
@ -1581,7 +1581,7 @@ r3d_setup(struct tu_cmd_buffer *cmd,
if (!cmd->state.pass) {
tu_emit_cache_flush_ccu<CHIP>(cmd, cs, TU_CMD_CCU_SYSMEM);
tu6_emit_window_scissor(cs, 0, 0, 0x3fff, 0x3fff);
if (cmd->device->physical_device->info->a7xx.has_hw_bin_scaling) {
if (cmd->device->physical_device->info->props.has_hw_bin_scaling) {
tu_cs_emit_regs(cs, A7XX_GRAS_BIN_FOVEAT());
tu_cs_emit_regs(cs, A7XX_RB_BIN_FOVEAT());
}
@ -3891,7 +3891,7 @@ use_generic_clear_for_image_clear(struct tu_cmd_buffer *cmd,
struct tu_image *image)
{
const struct fd_dev_info *info = cmd->device->physical_device->info;
return info->a7xx.has_generic_clear &&
return info->props.has_generic_clear &&
/* A7XX supports R9G9B9E5_FLOAT as color attachment and supports
* generic clears for it. A7XX TODO: allow R9G9B9E5_FLOAT
* attachments.
@ -3901,7 +3901,7 @@ use_generic_clear_for_image_clear(struct tu_cmd_buffer *cmd,
* dimensions (e.g. 960x540), and having GMEM renderpass afterwards
* may lead to a GPU fault on A7XX.
*/
!(info->a7xx.r8g8_faulty_fast_clear_quirk && image_is_r8g8(image));
!(info->props.r8g8_faulty_fast_clear_quirk && image_is_r8g8(image));
}
template <chip CHIP>
@ -4685,7 +4685,7 @@ tu_CmdClearAttachments(VkCommandBuffer commandBuffer,
tu_lrz_disable_during_renderpass<CHIP>(cmd, "CmdClearAttachments");
}
if (cmd->device->physical_device->info->a7xx.has_generic_clear &&
if (cmd->device->physical_device->info->props.has_generic_clear &&
/* Both having predication and not knowing layout could be solved
* by cs patching, which is exactly what prop driver is doing.
* We don't implement it because we don't expect a reasonable impact.

100
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -330,7 +330,7 @@ tu6_emit_flushes(struct tu_cmd_buffer *cmd_buffer,
!(flushes & TU_CMD_FLAG_CACHE_INVALIDATE))
tu_cs_emit_pkt7(cs, CP_CCHE_INVALIDATE, 0);
if (CHIP >= A7XX && (flushes & TU_CMD_FLAG_RTU_INVALIDATE) &&
cmd_buffer->device->physical_device->info->a7xx.has_rt_workaround)
cmd_buffer->device->physical_device->info->props.has_rt_workaround)
tu_emit_rt_workaround(cmd_buffer, cs);
if (flushes & TU_CMD_FLAG_WAIT_MEM_WRITES)
tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
@ -502,7 +502,7 @@ template <chip CHIP>
static void
emit_vpc_attr_buf(struct tu_cs *cs, struct tu_device *dev, bool gmem)
{
if (!dev->physical_device->info->a7xx.has_gmem_vpc_attr_buf)
if (!dev->physical_device->info->props.has_gmem_vpc_attr_buf)
return;
tu_cs_emit_regs(cs,
@ -556,7 +556,7 @@ emit_rb_ccu_cntl(struct tu_cs *cs, struct tu_device *dev, bool gmem)
depth_offset &= 0x1fffff;
enum a6xx_ccu_cache_size color_cache_size = !gmem ? CCU_CACHE_SIZE_FULL : !gmem ? CCU_CACHE_SIZE_FULL :
(a6xx_ccu_cache_size)(dev->physical_device->info->a6xx.gmem_ccu_color_cache_fraction);
(a6xx_ccu_cache_size)(dev->physical_device->info->props.gmem_ccu_color_cache_fraction);
if (CHIP == A7XX) {
tu_cs_emit_regs(cs, A7XX_RB_CCU_CACHE_CNTL(
@ -570,9 +570,9 @@ emit_rb_ccu_cntl(struct tu_cs *cs, struct tu_device *dev, bool gmem)
} else {
tu_cs_emit_regs(cs, RB_CCU_CNTL(CHIP,
.gmem_fast_clear_disable =
!dev->physical_device->info->a6xx.has_gmem_fast_clear,
!dev->physical_device->info->props.has_gmem_fast_clear,
.concurrent_resolve =
dev->physical_device->info->a6xx.concurrent_resolve,
dev->physical_device->info->props.concurrent_resolve,
.depth_offset_hi = 0,
.color_offset_hi = color_offset_hi,
.depth_cache_size = CCU_CACHE_SIZE_FULL,
@ -629,7 +629,7 @@ tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer,
if (ccu_state != cmd_buffer->state.ccu_state) {
emit_rb_ccu_cntl<CHIP>(cs, cmd_buffer->device,
ccu_state == TU_CMD_CCU_GMEM);
if (cmd_buffer->device->physical_device->info->a7xx.has_gmem_vpc_attr_buf) {
if (cmd_buffer->device->physical_device->info->props.has_gmem_vpc_attr_buf) {
tu7_thread_control(cs, CP_SET_THREAD_BOTH);
emit_vpc_attr_buf<CHIP>(cs, cmd_buffer->device,
@ -874,7 +874,7 @@ tu6_emit_render_cntl<A6XX>(struct tu_cmd_buffer *cmd,
bool binning)
{
/* doesn't RB_RENDER_CNTL set differently for binning pass: */
bool no_track = !cmd->device->physical_device->info->a6xx.has_cp_reg_write;
bool no_track = !cmd->device->physical_device->info->props.has_cp_reg_write;
uint32_t cntl = 0;
cntl |= A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(2);
if (binning) {
@ -1046,7 +1046,7 @@ void
tu6_apply_depth_bounds_workaround(struct tu_device *device,
uint32_t *rb_depth_cntl)
{
if (!device->physical_device->info->a6xx.depth_bounds_require_depth_test_quirk)
if (!device->physical_device->info->props.depth_bounds_require_depth_test_quirk)
return;
/* On some GPUs it is necessary to enable z test for depth bounds test when
@ -1088,7 +1088,7 @@ tu_cs_emit_draw_state(struct tu_cs *cs, uint32_t id, struct tu_draw_state state)
* longer depends on dynamic state, so we reuse the gmem state for
* everything:
*/
if (cs->device->physical_device->info->a6xx.has_coherent_ubwc_flag_caches) {
if (cs->device->physical_device->info->props.has_coherent_ubwc_flag_caches) {
enable_mask = CP_SET_DRAW_STATE__0_GMEM |
CP_SET_DRAW_STATE__0_SYSMEM |
CP_SET_DRAW_STATE__0_BINNING;
@ -1100,7 +1100,7 @@ tu_cs_emit_draw_state(struct tu_cs *cs, uint32_t id, struct tu_draw_state state)
enable_mask = CP_SET_DRAW_STATE__0_SYSMEM;
break;
case TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_PRIM_MODE_SYSMEM:
if (!cs->device->physical_device->info->a6xx.has_coherent_ubwc_flag_caches) {
if (!cs->device->physical_device->info->props.has_coherent_ubwc_flag_caches) {
/* By also applying the state during binning we ensure that there
* is no rotation applied, by previous A6XX_GRAS_SC_CNTL::rotation.
*/
@ -1449,7 +1449,7 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
}
bool bin_scale_en =
cmd->device->physical_device->info->a7xx.has_hw_bin_scaling &&
cmd->device->physical_device->info->props.has_hw_bin_scaling &&
views <= MAX_HW_SCALED_VIEWS && !cmd->state.rp.shared_viewport &&
bin_is_scaled;
@ -1468,10 +1468,10 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
cs, tiling->tile0.width, tiling->tile0.height,
{
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = !phys_dev->info->a6xx.has_lrz_feedback,
.force_lrz_write_dis = !phys_dev->info->props.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask =
phys_dev->info->a6xx.has_lrz_feedback && !bin_is_scaled
phys_dev->info->props.has_lrz_feedback && !bin_is_scaled
? (hw_binning ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z :
LRZ_FEEDBACK_EARLY_Z_LATE_Z)
: LRZ_FEEDBACK_NONE,
@ -1508,7 +1508,7 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
if (hw_binning) {
bool abs_mask =
cmd->device->physical_device->info->a7xx.has_abs_bin_mask;
cmd->device->physical_device->info->props.has_abs_bin_mask;
tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
@ -1561,7 +1561,7 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
MAX2(MIN2((int32_t)y1 + bin.extent.height - bin_offset.y, MAX_VIEWPORT_SIZE) - bins[i].offset.y, 0);
}
if (cmd->device->physical_device->info->a7xx.has_hw_bin_scaling) {
if (cmd->device->physical_device->info->props.has_hw_bin_scaling) {
if (bin_scale_en) {
VkExtent2D frag_areas[MAX_HW_SCALED_VIEWS];
for (unsigned i = 0; i < MAX_HW_SCALED_VIEWS; i++) {
@ -1634,7 +1634,7 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
tu_cs_emit_wfi(cs);
}
tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
} else if (cmd->device->physical_device->info->a7xx.has_hw_bin_scaling) {
} else if (cmd->device->physical_device->info->props.has_hw_bin_scaling) {
tu_cs_emit_regs(cs, A7XX_GRAS_BIN_FOVEAT());
tu_cs_emit_regs(cs, A7XX_RB_BIN_FOVEAT());
}
@ -1930,14 +1930,14 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
tu_cs_emit_regs(cs, RB_CCU_CNTL(A7XX,
.gmem_fast_clear_disable =
!dev->physical_device->info->a6xx.has_gmem_fast_clear,
!dev->physical_device->info->props.has_gmem_fast_clear,
.concurrent_resolve_mode = resolve_mode,
.concurrent_unresolve_mode = unresolve_mode,
));
}
for (size_t i = 0; i < ARRAY_SIZE(phys_dev->info->a6xx.magic_raw); i++) {
auto magic_reg = phys_dev->info->a6xx.magic_raw[i];
for (size_t i = 0; i < ARRAY_SIZE(phys_dev->info->props.magic_raw); i++) {
auto magic_reg = phys_dev->info->props.magic_raw[i];
if (!magic_reg.reg)
break;
@ -1945,7 +1945,7 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
switch(magic_reg.reg) {
case REG_A6XX_TPL1_DBG_ECO_CNTL1:
value = (value & ~A6XX_TPL1_DBG_ECO_CNTL1_TP_UBWC_FLAG_HINT) |
(phys_dev->info->a7xx.enable_tp_ubwc_flag_hint
(phys_dev->info->props.enable_tp_ubwc_flag_hint
? A6XX_TPL1_DBG_ECO_CNTL1_TP_UBWC_FLAG_HINT
: 0);
break;
@ -1954,7 +1954,7 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
tu_cs_emit_write_reg(cs, magic_reg.reg, value);
}
if (dev->physical_device->info->a6xx.has_attachment_shading_rate) {
if (dev->physical_device->info->props.has_attachment_shading_rate) {
tu_cs_emit_write_reg(cs, REG_A7XX_GRAS_LRZ_QUALITY_LOOKUP_TABLE(0),
fd_gras_shading_rate_lut(0));
tu_cs_emit_write_reg(cs, REG_A7XX_GRAS_LRZ_QUALITY_LOOKUP_TABLE(1),
@ -1963,7 +1963,7 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
tu_cs_emit_write_reg(cs, REG_A6XX_SP_NC_MODE_CNTL_2, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x3f);
if (CHIP == A6XX && !cs->device->physical_device->info->a6xx.is_a702)
if (CHIP == A6XX && !cs->device->physical_device->info->props.is_a702)
tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
if (CHIP == A6XX) {
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
@ -2038,9 +2038,9 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(THREAD_MODE) |
CP_COND_REG_EXEC_0_BR);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_DBG_ECO_CNTL,
phys_dev->info->a6xx.magic.RB_DBG_ECO_CNTL);
phys_dev->info->props.magic.RB_DBG_ECO_CNTL);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_RBP_CNTL,
phys_dev->info->a6xx.magic.RB_RBP_CNTL);
phys_dev->info->props.magic.RB_RBP_CNTL);
if (CHIP >= A7XX)
tu_cond_exec_end(cs);
@ -2077,7 +2077,7 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
* so any leftover early preamble doesn't get executed. Other stages don't
* seem to be affected.
*/
if (phys_dev->info->a6xx.has_early_preamble) {
if (phys_dev->info->props.has_early_preamble) {
tu_cs_emit_regs(cs, A6XX_SP_PS_CNTL_0());
}
@ -2211,7 +2211,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_disable_draw_states(cmd, cs);
if (phys_dev->info->a7xx.cmdbuf_start_a725_quirk) {
if (phys_dev->info->props.cmdbuf_start_a725_quirk) {
tu_cs_reserve(cs, 3 + 4);
tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(THREAD_MODE) |
@ -2578,7 +2578,7 @@ tu_emit_input_attachments(struct tu_cmd_buffer *cmd,
A6XX_TEX_CONST_0_SWAP__MASK |
A6XX_TEX_CONST_0_SWIZ_X__MASK | A6XX_TEX_CONST_0_SWIZ_Y__MASK |
A6XX_TEX_CONST_0_SWIZ_Z__MASK | A6XX_TEX_CONST_0_SWIZ_W__MASK);
if (!cmd->device->physical_device->info->a6xx.has_z24uint_s8uint) {
if (!cmd->device->physical_device->info->props.has_z24uint_s8uint) {
dst[0] |= A6XX_TEX_CONST_0_FMT(FMT6_8_8_8_8_UINT) |
A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_W) |
A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO) |
@ -2961,10 +2961,10 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
tu6_emit_bin_size<CHIP>(cs, 0, 0, {
.render_mode = RENDERING_PASS,
.force_lrz_write_dis =
!cmd->device->physical_device->info->a6xx.has_lrz_feedback,
!cmd->device->physical_device->info->props.has_lrz_feedback,
.buffers_location = BUFFERS_IN_SYSMEM,
.lrz_feedback_zmode_mask =
cmd->device->physical_device->info->a6xx.has_lrz_feedback
cmd->device->physical_device->info->props.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE,
});
@ -3005,7 +3005,7 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
tu_cs_emit(cs, 0x0);
/* Reset bin scaling. */
if (cmd->device->physical_device->info->a7xx.has_hw_bin_scaling) {
if (cmd->device->physical_device->info->props.has_hw_bin_scaling) {
tu_cs_emit_regs(cs, A7XX_GRAS_BIN_FOVEAT());
tu_cs_emit_regs(cs, A7XX_RB_BIN_FOVEAT());
}
@ -3229,7 +3229,7 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
tu_cs_emit(cs, 0x0);
/* Reset bin scaling. */
if (phys_dev->info->a7xx.has_hw_bin_scaling) {
if (phys_dev->info->props.has_hw_bin_scaling) {
tu_cs_emit_regs(cs, A7XX_GRAS_BIN_FOVEAT());
tu_cs_emit_regs(cs, A7XX_RB_BIN_FOVEAT());
}
@ -3265,7 +3265,7 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
.render_mode = BINNING_PASS,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask =
phys_dev->info->a6xx.has_lrz_feedback
phys_dev->info->props.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE
});
@ -3723,7 +3723,7 @@ tu_render_pipe_fdm(struct tu_cmd_buffer *cmd, uint32_t pipe,
uint32_t height = ty2 - ty1;
unsigned views = tu_fdm_num_layers(cmd);
bool has_abs_mask =
cmd->device->physical_device->info->a7xx.has_abs_bin_mask;
cmd->device->physical_device->info->props.has_abs_bin_mask;
struct tu_tile_config tiles[width * height];
@ -3832,7 +3832,7 @@ tu_cmd_render_tiles(struct tu_cmd_buffer *cmd,
bool has_fdm = fdm || (TU_DEBUG(FDM) && cmd->state.pass->has_fdm);
bool merge_tiles = has_fdm && !TU_DEBUG(NO_BIN_MERGING) &&
cmd->device->physical_device->info->a6xx.has_bin_mask;
cmd->device->physical_device->info->props.has_bin_mask;
/* If not using FDM make sure not to accidentally apply the offsets */
if (!has_fdm)
@ -6436,7 +6436,7 @@ tu_emit_subpass_begin_gmem(struct tu_cmd_buffer *cmd, struct tu_resolve_group *r
cond_load_allowed, true);
}
if (!cmd->device->physical_device->info->a7xx.has_generic_clear) {
if (!cmd->device->physical_device->info->props.has_generic_clear) {
/* Emit gmem clears that are first used in this subpass. */
emitted_scissor = false;
for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i) {
@ -6464,7 +6464,7 @@ template <chip CHIP>
static void
tu_emit_subpass_begin_sysmem(struct tu_cmd_buffer *cmd)
{
if (cmd->device->physical_device->info->a7xx.has_generic_clear &&
if (cmd->device->physical_device->info->props.has_generic_clear &&
!cmd->state.subpass->unresolve_count)
return;
@ -6574,7 +6574,7 @@ tu_emit_subpass_begin(struct tu_cmd_buffer *cmd)
tu_emit_subpass_begin_gmem<CHIP>(cmd, &resolve_group);
tu_emit_subpass_begin_sysmem<CHIP>(cmd);
if (cmd->device->physical_device->info->a7xx.has_generic_clear) {
if (cmd->device->physical_device->info->props.has_generic_clear) {
tu7_emit_subpass_clear(cmd, &resolve_group);
}
@ -6835,7 +6835,7 @@ tu_CmdBeginRendering(VkCommandBuffer commandBuffer,
* disable LRZ when resuming/suspending unless we can track on the GPU.
*/
if ((resuming || suspending) &&
!cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking) {
!cmd->device->physical_device->info->props.has_lrz_dir_tracking) {
cmd->state.lrz.valid = false;
} else {
if (resuming)
@ -7099,7 +7099,7 @@ tu6_emit_inline_ubo(struct tu_cs *cs,
mesa_shader_stage type,
struct tu_descriptor_state *descriptors)
{
assert(const_state->num_inline_ubos == 0 || !cs->device->physical_device->info->a7xx.load_shader_consts_via_preamble);
assert(const_state->num_inline_ubos == 0 || !cs->device->physical_device->info->props.load_shader_consts_via_preamble);
/* Emit loads of inline uniforms. These load directly from the uniform's
* storage space inside the descriptor set.
@ -7177,7 +7177,7 @@ tu_emit_inline_ubo(struct tu_cs *cs,
if (!const_state->num_inline_ubos)
return;
if (cs->device->physical_device->info->a7xx.load_inline_uniforms_via_preamble_ldgk) {
if (cs->device->physical_device->info->props.load_inline_uniforms_via_preamble_ldgk) {
tu7_emit_inline_ubo(cs, const_state, ir_const_state, constlen, type, descriptors);
} else {
tu6_emit_inline_ubo(cs, const_state, constlen, type, descriptors);
@ -7237,7 +7237,7 @@ tu6_const_size(struct tu_cmd_buffer *cmd,
dwords += shared_consts->dwords + 1;
}
bool ldgk = cmd->device->physical_device->info->a7xx.load_inline_uniforms_via_preamble_ldgk;
bool ldgk = cmd->device->physical_device->info->props.load_inline_uniforms_via_preamble_ldgk;
if (compute) {
dwords +=
tu6_user_consts_size(&cmd->state.shaders[MESA_SHADER_COMPUTE]->const_state, ldgk, MESA_SHADER_COMPUTE);
@ -7846,7 +7846,7 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
tess_params->output_lower_left));
}
if (cmd->device->physical_device->info->a7xx.has_rt_workaround &&
if (cmd->device->physical_device->info->props.has_rt_workaround &&
cmd->state.program.uses_ray_intersection) {
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_SHADER_USES_RT);
@ -7881,7 +7881,7 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
if (dirty_lrz) {
struct tu_cs cs;
uint32_t size = 8 +
(cmd->device->physical_device->info->a6xx.lrz_track_quirk ? 2 : 0) +
(cmd->device->physical_device->info->props.lrz_track_quirk ? 2 : 0) +
(CHIP >= A7XX ? 2 : 0); // A7XX has extra packets from LRZ_CNTL2.
cmd->state.lrz_and_depth_plane_state =
@ -8097,7 +8097,7 @@ tu6_emit_empty_vs_params(struct tu_cmd_buffer *cmd)
if (cmd->state.last_vs_params.empty)
return;
if (cmd->device->physical_device->info->a7xx.load_shader_consts_via_preamble) {
if (cmd->device->physical_device->info->props.load_shader_consts_via_preamble) {
struct tu_cs cs;
cmd->state.vs_params = tu_cs_draw_state(&cmd->sub_cs, &cs, 2);
@ -8373,7 +8373,7 @@ tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
tu6_emit_empty_vs_params<CHIP>(cmd);
if (cmd->device->physical_device->info->a6xx.indirect_draw_wfm_quirk)
if (cmd->device->physical_device->info->props.indirect_draw_wfm_quirk)
draw_wfm(cmd);
tu6_draw_common<CHIP>(cmd, cs, false, 0);
@ -8404,7 +8404,7 @@ tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
tu6_emit_empty_vs_params<CHIP>(cmd);
if (cmd->device->physical_device->info->a6xx.indirect_draw_wfm_quirk)
if (cmd->device->physical_device->info->props.indirect_draw_wfm_quirk)
draw_wfm(cmd);
tu6_draw_common<CHIP>(cmd, cs, true, 0);
@ -8599,7 +8599,7 @@ tu_emit_compute_driver_params(struct tu_cmd_buffer *cmd,
unsigned subgroup_size = variant->info.subgroup_size;
unsigned subgroup_shift = util_logbase2(subgroup_size);
if (cmd->device->physical_device->info->a7xx.load_shader_consts_via_preamble) {
if (cmd->device->physical_device->info->props.load_shader_consts_via_preamble) {
uint32_t num_consts = const_state->driver_params_ubo.size;
if (num_consts == 0)
return;
@ -8784,7 +8784,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
bool emit_instrlen_workaround =
shader->variant->instrlen >
cmd->device->physical_device->info->a6xx.instr_cache_size;
cmd->device->physical_device->info->props.instr_cache_size;
/* We don't use draw states for dispatches, so the bound pipeline
* could be overwritten by reg stomping in a renderpass or blit.
@ -8990,7 +8990,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
}
}
if (cmd->device->physical_device->info->a7xx.has_rt_workaround &&
if (cmd->device->physical_device->info->props.has_rt_workaround &&
shader->variant->info.uses_ray_intersection) {
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_SHADER_USES_RT);
@ -9413,7 +9413,7 @@ tu_barrier(struct tu_cmd_buffer *cmd,
* we can't use that to insert the flush. Instead we use the shader source
* stage.
*/
if (cmd->device->physical_device->info->a7xx.ubwc_coherency_quirk &&
if (cmd->device->physical_device->info->props.ubwc_coherency_quirk &&
(srcStage &
(VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT |
VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT |

22
src/freedreno/vulkan/tu_descriptor_set.cc
View file

@ -62,9 +62,9 @@ descriptor_size(struct tu_device *dev,
* two separate descriptors are required.
*/
return A6XX_TEX_CONST_DWORDS * 4 * (1 +
COND(dev->physical_device->info->a6xx.storage_16bit &&
!dev->physical_device->info->a6xx.has_isam_v, 1) +
COND(dev->physical_device->info->a7xx.storage_8bit, 1));
COND(dev->physical_device->info->props.storage_16bit &&
!dev->physical_device->info->props.has_isam_v, 1) +
COND(dev->physical_device->info->props.storage_8bit, 1));
case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK:
return binding->descriptorCount;
case VK_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE_KHR:
@ -988,18 +988,18 @@ write_buffer_descriptor_addr(const struct tu_device *device,
/* This prevents any misconfiguration, but 16-bit descriptor capable of both
* 16-bit and 32-bit access through isam.v will of course only be functional
* when 16-bit storage is supported. */
assert(!info->a6xx.has_isam_v || info->a6xx.storage_16bit);
assert(!info->props.has_isam_v || info->props.storage_16bit);
/* Any configuration enabling 8-bit storage support will also provide 16-bit
* storage support and 16-bit descriptors capable of 32-bit isam loads. This
* indirectly ensures we won't need more than two descriptors for access of
* any size.
*/
assert(!info->a7xx.storage_8bit || (info->a6xx.storage_16bit &&
info->a6xx.has_isam_v));
assert(!info->props.storage_8bit || (info->props.storage_16bit &&
info->props.has_isam_v));
unsigned num_descriptors = 1 +
COND(info->a6xx.storage_16bit && !info->a6xx.has_isam_v, 1) +
COND(info->a7xx.storage_8bit, 1);
COND(info->props.storage_16bit && !info->props.has_isam_v, 1) +
COND(info->props.storage_8bit, 1);
memset(dst, 0, num_descriptors * A6XX_TEX_CONST_DWORDS * sizeof(uint32_t));
if (!buffer_info || buffer_info->address == 0)
@ -1010,7 +1010,7 @@ write_buffer_descriptor_addr(const struct tu_device *device,
unsigned offset = va & 0x3f;
uint32_t range = buffer_info->range;
if (info->a6xx.storage_16bit) {
if (info->props.storage_16bit) {
dst[0] = A6XX_TEX_CONST_0_TILE_MODE(TILE6_LINEAR) | A6XX_TEX_CONST_0_FMT(FMT6_16_UINT);
dst[1] = DIV_ROUND_UP(range, 2);
dst[2] =
@ -1025,7 +1025,7 @@ write_buffer_descriptor_addr(const struct tu_device *device,
/* Set up the 32-bit descriptor when 16-bit storage isn't supported or the
* 16-bit descriptor cannot be used for 32-bit loads through isam.v.
*/
if (!info->a6xx.storage_16bit || !info->a6xx.has_isam_v) {
if (!info->props.storage_16bit || !info->props.has_isam_v) {
dst[0] = A6XX_TEX_CONST_0_TILE_MODE(TILE6_LINEAR) | A6XX_TEX_CONST_0_FMT(FMT6_32_UINT);
dst[1] = DIV_ROUND_UP(range, 4);
dst[2] =
@ -1037,7 +1037,7 @@ write_buffer_descriptor_addr(const struct tu_device *device,
dst += A6XX_TEX_CONST_DWORDS;
}
if (info->a7xx.storage_8bit) {
if (info->props.storage_8bit) {
dst[0] = A6XX_TEX_CONST_0_TILE_MODE(TILE6_LINEAR) | A6XX_TEX_CONST_0_FMT(FMT6_8_UINT);
dst[1] = range;
dst[2] =

142
src/freedreno/vulkan/tu_device.cc
View file

@ -143,7 +143,7 @@ is_kgsl(struct tu_instance *instance)
static bool tu_has_multiview(const struct tu_physical_device *device)
{
return device->info->a6xx.has_hw_multiview || TU_DEBUG(NOCONFORM);
return device->info->props.has_hw_multiview || TU_DEBUG(NOCONFORM);
}
/* We are generally VK 1.1 except A702, which has no multiview */
@ -162,16 +162,16 @@ get_device_extensions(const struct tu_physical_device *device,
* fuse is set and we have ray_intersection.
*/
bool has_raytracing =
device->info->a7xx.has_ray_intersection &&
(!device->info->a7xx.has_sw_fuse || device->has_raytracing);
device->info->props.has_ray_intersection &&
(!device->info->props.has_sw_fuse || device->has_raytracing);
*ext = (struct vk_device_extension_table) { .table = {
.KHR_8bit_storage = device->info->a7xx.storage_8bit,
.KHR_16bit_storage = device->info->a6xx.storage_16bit,
.KHR_8bit_storage = device->info->props.storage_8bit,
.KHR_16bit_storage = device->info->props.storage_16bit,
.KHR_acceleration_structure = has_raytracing,
.KHR_bind_memory2 = true,
.KHR_buffer_device_address = true,
.KHR_calibrated_timestamps = device->info->a7xx.has_persistent_counter,
.KHR_calibrated_timestamps = device->info->props.has_persistent_counter,
.KHR_compute_shader_derivatives = device->info->chip >= 7,
.KHR_copy_commands2 = true,
// TODO workaround for https://github.com/KhronosGroup/VK-GL-CTS/issues/525
@ -192,7 +192,7 @@ get_device_extensions(const struct tu_physical_device *device,
.KHR_external_semaphore = true,
.KHR_external_semaphore_fd = true,
.KHR_format_feature_flags2 = true,
.KHR_fragment_shading_rate = device->info->a6xx.has_attachment_shading_rate,
.KHR_fragment_shading_rate = device->info->props.has_attachment_shading_rate,
.KHR_get_memory_requirements2 = true,
.KHR_global_priority = tu_is_vk_1_1(device),
.KHR_image_format_list = true,
@ -201,7 +201,7 @@ get_device_extensions(const struct tu_physical_device *device,
.KHR_incremental_present = true,
#endif
.KHR_index_type_uint8 = true,
.KHR_line_rasterization = !device->info->a6xx.is_a702,
.KHR_line_rasterization = !device->info->props.is_a702,
.KHR_load_store_op_none = true,
.KHR_maintenance1 = true,
.KHR_maintenance2 = true,
@ -229,7 +229,7 @@ get_device_extensions(const struct tu_physical_device *device,
.KHR_sampler_mirror_clamp_to_edge = true,
.KHR_sampler_ycbcr_conversion = true,
.KHR_separate_depth_stencil_layouts = true,
.KHR_shader_atomic_int64 = device->info->a7xx.has_64b_ssbo_atomics,
.KHR_shader_atomic_int64 = device->info->props.has_64b_ssbo_atomics,
.KHR_shader_clock = true,
.KHR_shader_draw_parameters = true,
.KHR_shader_expect_assume = true,
@ -263,7 +263,7 @@ get_device_extensions(const struct tu_physical_device *device,
.EXT_attachment_feedback_loop_dynamic_state = true,
.EXT_attachment_feedback_loop_layout = true,
.EXT_border_color_swizzle = true,
.EXT_calibrated_timestamps = device->info->a7xx.has_persistent_counter,
.EXT_calibrated_timestamps = device->info->props.has_persistent_counter,
.EXT_color_write_enable = true,
.EXT_conditional_rendering = true,
.EXT_conservative_rasterization = device->info->chip >= 7,
@ -282,7 +282,7 @@ get_device_extensions(const struct tu_physical_device *device,
.EXT_extended_dynamic_state2 = true,
.EXT_extended_dynamic_state3 = true,
.EXT_external_memory_dma_buf = true,
.EXT_filter_cubic = device->info->a6xx.has_tex_filter_cubic,
.EXT_filter_cubic = device->info->props.has_tex_filter_cubic,
.EXT_fragment_density_map = true,
.EXT_fragment_density_map_offset = true,
.EXT_global_priority = tu_is_vk_1_1(device),
@ -318,8 +318,8 @@ get_device_extensions(const struct tu_physical_device *device,
.EXT_queue_family_foreign = true,
.EXT_rasterization_order_attachment_access = true,
.EXT_robustness2 = true,
.EXT_sample_locations = device->info->a6xx.has_sample_locations,
.EXT_sampler_filter_minmax = device->info->a6xx.has_sampler_minmax,
.EXT_sample_locations = device->info->props.has_sample_locations,
.EXT_sampler_filter_minmax = device->info->props.has_sampler_minmax,
.EXT_scalar_block_layout = true,
.EXT_separate_stencil_usage = true,
.EXT_shader_atomic_float = true,
@ -345,7 +345,7 @@ get_device_extensions(const struct tu_physical_device *device,
.GOOGLE_decorate_string = true,
.GOOGLE_hlsl_functionality1 = true,
.GOOGLE_user_type = true,
.IMG_filter_cubic = device->info->a6xx.has_tex_filter_cubic,
.IMG_filter_cubic = device->info->props.has_tex_filter_cubic,
.NV_compute_shader_derivatives = device->info->chip >= 7,
.QCOM_fragment_density_map_offset = true,
.VALVE_fragment_density_map_layered = true,
@ -371,18 +371,18 @@ tu_get_features(struct tu_physical_device *pdevice,
features->fullDrawIndexUint32 = true;
features->imageCubeArray = true;
features->independentBlend = true;
features->geometryShader = !pdevice->info->a6xx.is_a702;
features->tessellationShader = !pdevice->info->a6xx.is_a702;
features->geometryShader = !pdevice->info->props.is_a702;
features->tessellationShader = !pdevice->info->props.is_a702;
features->sampleRateShading = true;
features->dualSrcBlend = true;
features->logicOp = true;
features->multiDrawIndirect = true;
features->drawIndirectFirstInstance = true;
features->depthClamp = true;
features->depthBiasClamp = !pdevice->info->a6xx.is_a702;
features->depthBiasClamp = !pdevice->info->props.is_a702;
features->fillModeNonSolid = true;
features->depthBounds = true;
features->wideLines = pdevice->info->a6xx.line_width_max > 1.0;
features->wideLines = pdevice->info->props.line_width_max > 1.0;
features->largePoints = true;
features->alphaToOne = true;
features->multiViewport = tu_has_multiview(pdevice);
@ -390,12 +390,12 @@ tu_get_features(struct tu_physical_device *pdevice,
features->textureCompressionETC2 = true;
features->textureCompressionASTC_LDR = true;
/* no BC6H & BC7 support on A702 */
features->textureCompressionBC = !pdevice->info->a6xx.is_a702;
features->textureCompressionBC = !pdevice->info->props.is_a702;
features->occlusionQueryPrecise = true;
features->pipelineStatisticsQuery = true;
features->vertexPipelineStoresAndAtomics = true;
features->fragmentStoresAndAtomics = true;
features->shaderTessellationAndGeometryPointSize = !pdevice->info->a6xx.is_a702;
features->shaderTessellationAndGeometryPointSize = !pdevice->info->props.is_a702;
features->shaderImageGatherExtended = true;
features->shaderStorageImageExtendedFormats = true;
features->shaderStorageImageMultisample = false;
@ -413,7 +413,7 @@ tu_get_features(struct tu_physical_device *pdevice,
features->sparseBinding = pdevice->has_sparse;
features->sparseResidencyBuffer = pdevice->has_sparse_prr;
features->sparseResidencyImage2D = pdevice->has_sparse_prr &&
pdevice->info->a7xx.ubwc_all_formats_compatible;
pdevice->info->props.ubwc_all_formats_compatible;
features->sparseResidency2Samples = features->sparseResidencyImage2D;
features->sparseResidency4Samples = features->sparseResidencyImage2D;
features->sparseResidency8Samples = features->sparseResidencyImage2D;
@ -424,7 +424,7 @@ tu_get_features(struct tu_physical_device *pdevice,
features->inheritedQueries = true;
/* Vulkan 1.1 */
features->storageBuffer16BitAccess = pdevice->info->a6xx.storage_16bit;
features->storageBuffer16BitAccess = pdevice->info->props.storage_16bit;
features->uniformAndStorageBuffer16BitAccess = false;
features->storagePushConstant16 = false;
features->storageInputOutput16 = false;
@ -440,11 +440,11 @@ tu_get_features(struct tu_physical_device *pdevice,
/* Vulkan 1.2 */
features->samplerMirrorClampToEdge = true;
features->drawIndirectCount = true;
features->storageBuffer8BitAccess = pdevice->info->a7xx.storage_8bit;
features->storageBuffer8BitAccess = pdevice->info->props.storage_8bit;
features->uniformAndStorageBuffer8BitAccess = false;
features->storagePushConstant8 = false;
features->shaderBufferInt64Atomics =
pdevice->info->a7xx.has_64b_ssbo_atomics;
pdevice->info->props.has_64b_ssbo_atomics;
features->shaderSharedInt64Atomics = false;
features->shaderFloat16 = true;
features->shaderInt8 = true;
@ -472,7 +472,7 @@ tu_get_features(struct tu_physical_device *pdevice,
features->runtimeDescriptorArray = true;
features->samplerFilterMinmax =
pdevice->info->a6xx.has_sampler_minmax;
pdevice->info->props.has_sampler_minmax;
features->scalarBlockLayout = true;
features->imagelessFramebuffer = true;
features->uniformBufferStandardLayout = true;
@ -523,15 +523,15 @@ tu_get_features(struct tu_physical_device *pdevice,
features->dynamicRenderingLocalRead = true;
/* VK_KHR_fragment_shading_rate */
features->pipelineFragmentShadingRate = pdevice->info->a6xx.has_attachment_shading_rate;
features->primitiveFragmentShadingRate = pdevice->info->a7xx.has_primitive_shading_rate;
features->attachmentFragmentShadingRate = pdevice->info->a6xx.has_attachment_shading_rate;
features->pipelineFragmentShadingRate = pdevice->info->props.has_attachment_shading_rate;
features->primitiveFragmentShadingRate = pdevice->info->props.has_primitive_shading_rate;
features->attachmentFragmentShadingRate = pdevice->info->props.has_attachment_shading_rate;
/* VK_KHR_index_type_uint8 */
features->indexTypeUint8 = true;
/* VK_KHR_line_rasterization */
features->rectangularLines = !pdevice->info->a6xx.is_a702;
features->rectangularLines = !pdevice->info->props.is_a702;
features->bresenhamLines = true;
features->smoothLines = false;
features->stippledRectangularLines = false;
@ -641,7 +641,7 @@ tu_get_features(struct tu_physical_device *pdevice,
/* VK_EXT_extended_dynamic_state3 */
features->extendedDynamicState3PolygonMode = true;
features->extendedDynamicState3TessellationDomainOrigin = !pdevice->info->a6xx.is_a702;
features->extendedDynamicState3TessellationDomainOrigin = !pdevice->info->props.is_a702;
features->extendedDynamicState3DepthClampEnable = true;
features->extendedDynamicState3DepthClipEnable = true;
features->extendedDynamicState3LogicOpEnable = true;
@ -650,7 +650,7 @@ tu_get_features(struct tu_physical_device *pdevice,
features->extendedDynamicState3AlphaToCoverageEnable = true;
features->extendedDynamicState3AlphaToOneEnable = true;
features->extendedDynamicState3DepthClipNegativeOneToOne = true;
features->extendedDynamicState3RasterizationStream = !pdevice->info->a6xx.is_a702;
features->extendedDynamicState3RasterizationStream = !pdevice->info->props.is_a702;
features->extendedDynamicState3ConservativeRasterizationMode =
pdevice->vk.supported_extensions.EXT_conservative_rasterization;
features->extendedDynamicState3ExtraPrimitiveOverestimationSize =
@ -659,7 +659,7 @@ tu_get_features(struct tu_physical_device *pdevice,
features->extendedDynamicState3LineStippleEnable = false;
features->extendedDynamicState3ProvokingVertexMode = true;
features->extendedDynamicState3SampleLocationsEnable =
pdevice->info->a6xx.has_sample_locations;
pdevice->info->props.has_sample_locations;
features->extendedDynamicState3ColorBlendEnable = true;
features->extendedDynamicState3ColorBlendEquation = true;
features->extendedDynamicState3ColorWriteMask = true;
@ -788,7 +788,7 @@ tu_get_features(struct tu_physical_device *pdevice,
/* VK_EXT_transform_feedback */
features->transformFeedback = true;
features->geometryStreams = !pdevice->info->a6xx.is_a702;
features->geometryStreams = !pdevice->info->props.is_a702;
/* VK_EXT_vertex_input_dynamic_state */
features->vertexInputDynamicState = true;
@ -830,7 +830,7 @@ tu_get_physical_device_properties_1_1(struct tu_physical_device *pdevice,
p->deviceNodeMask = 0;
p->deviceLUIDValid = false;
p->subgroupSize = pdevice->info->a6xx.supports_double_threadsize ?
p->subgroupSize = pdevice->info->props.supports_double_threadsize ?
pdevice->info->threadsize_base * 2 : pdevice->info->threadsize_base;
p->subgroupSupportedStages = VK_SHADER_STAGE_COMPUTE_BIT;
p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
@ -842,7 +842,7 @@ tu_get_physical_device_properties_1_1(struct tu_physical_device *pdevice,
VK_SUBGROUP_FEATURE_ROTATE_CLUSTERED_BIT_KHR |
VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
VK_SUBGROUP_FEATURE_ARITHMETIC_BIT;
if (pdevice->info->a6xx.has_getfiberid) {
if (pdevice->info->props.has_getfiberid) {
p->subgroupSupportedStages |= VK_SHADER_STAGE_ALL_GRAPHICS;
p->subgroupSupportedOperations |= VK_SUBGROUP_FEATURE_QUAD_BIT;
}
@ -970,7 +970,7 @@ tu_get_physical_device_properties_1_3(struct tu_physical_device *pdevice,
struct vk_properties *p)
{
p->minSubgroupSize = pdevice->info->threadsize_base;
p->maxSubgroupSize = pdevice->info->a6xx.supports_double_threadsize ?
p->maxSubgroupSize = pdevice->info->props.supports_double_threadsize ?
pdevice->info->threadsize_base * 2 : pdevice->info->threadsize_base;
p->maxComputeWorkgroupSubgroups = pdevice->info->max_waves;
p->requiredSubgroupSizeStages = VK_SHADER_STAGE_ALL;
@ -986,11 +986,11 @@ tu_get_physical_device_properties_1_3(struct tu_physical_device *pdevice,
p->integerDotProduct8BitSignedAccelerated = false;
p->integerDotProduct8BitMixedSignednessAccelerated = false;
p->integerDotProduct4x8BitPackedUnsignedAccelerated =
pdevice->info->a6xx.has_dp2acc;
pdevice->info->props.has_dp2acc;
/* TODO: we should be able to emulate 4x8BitPackedSigned fast enough */
p->integerDotProduct4x8BitPackedSignedAccelerated = false;
p->integerDotProduct4x8BitPackedMixedSignednessAccelerated =
pdevice->info->a6xx.has_dp2acc;
pdevice->info->props.has_dp2acc;
p->integerDotProduct16BitUnsignedAccelerated = false;
p->integerDotProduct16BitSignedAccelerated = false;
p->integerDotProduct16BitMixedSignednessAccelerated = false;
@ -1004,11 +1004,11 @@ tu_get_physical_device_properties_1_3(struct tu_physical_device *pdevice,
p->integerDotProductAccumulatingSaturating8BitSignedAccelerated = false;
p->integerDotProductAccumulatingSaturating8BitMixedSignednessAccelerated = false;
p->integerDotProductAccumulatingSaturating4x8BitPackedUnsignedAccelerated =
pdevice->info->a6xx.has_dp2acc;
pdevice->info->props.has_dp2acc;
/* TODO: we should be able to emulate Saturating4x8BitPackedSigned fast enough */
p->integerDotProductAccumulatingSaturating4x8BitPackedSignedAccelerated = false;
p->integerDotProductAccumulatingSaturating4x8BitPackedMixedSignednessAccelerated =
pdevice->info->a6xx.has_dp2acc;
pdevice->info->props.has_dp2acc;
p->integerDotProductAccumulatingSaturating16BitUnsignedAccelerated = false;
p->integerDotProductAccumulatingSaturating16BitSignedAccelerated = false;
p->integerDotProductAccumulatingSaturating16BitMixedSignednessAccelerated = false;
@ -1044,7 +1044,7 @@ tu_get_properties(struct tu_physical_device *pdevice,
props->maxImageDimension2D = (1 << 14);
props->maxImageDimension3D = (1 << 11);
props->maxImageDimensionCube = (1 << 14);
props->maxImageArrayLayers = (1 << (pdevice->info->a6xx.is_a702 ? 8 : 11));
props->maxImageArrayLayers = (1 << (pdevice->info->props.is_a702 ? 8 : 11));
props->maxTexelBufferElements = MAX_TEXEL_ELEMENTS;
props->maxUniformBufferRange = MAX_UNIFORM_BUFFER_RANGE;
props->maxStorageBufferRange = MAX_STORAGE_BUFFER_RANGE;
@ -1069,12 +1069,12 @@ tu_get_properties(struct tu_physical_device *pdevice,
props->maxDescriptorSetSampledImages = max_descriptor_set_size;
props->maxDescriptorSetStorageImages = max_descriptor_set_size;
props->maxDescriptorSetInputAttachments = MAX_RTS;
props->maxVertexInputAttributes = pdevice->info->a6xx.vs_max_inputs_count;
props->maxVertexInputBindings = pdevice->info->a6xx.vs_max_inputs_count;
props->maxVertexInputAttributes = pdevice->info->props.vs_max_inputs_count;
props->maxVertexInputBindings = pdevice->info->props.vs_max_inputs_count;
props->maxVertexInputAttributeOffset = 4095;
props->maxVertexInputBindingStride = 2048;
props->maxVertexOutputComponents = pdevice->info->a6xx.is_a702 ? 64 : 128;
if (!pdevice->info->a6xx.is_a702) {
props->maxVertexOutputComponents = pdevice->info->props.is_a702 ? 64 : 128;
if (!pdevice->info->props.is_a702) {
props->maxTessellationGenerationLevel = 64;
props->maxTessellationPatchSize = 32;
props->maxTessellationControlPerVertexInputComponents = 128;
@ -1091,7 +1091,7 @@ tu_get_properties(struct tu_physical_device *pdevice,
}
// probably should be props->maxVertexOutputComponents - 4 but that is
// below the limit on a702
props->maxFragmentInputComponents = pdevice->info->a6xx.is_a702 ? 112 : 124;
props->maxFragmentInputComponents = pdevice->info->props.is_a702 ? 112 : 124;
props->maxFragmentOutputAttachments = 8;
props->maxFragmentDualSrcAttachments = 1;
props->maxFragmentCombinedOutputResources = MAX_RTS + max_descriptor_set_size * 2;
@ -1099,10 +1099,10 @@ tu_get_properties(struct tu_physical_device *pdevice,
props->maxComputeWorkGroupCount[0] =
props->maxComputeWorkGroupCount[1] =
props->maxComputeWorkGroupCount[2] = 65535;
props->maxComputeWorkGroupInvocations = pdevice->info->a6xx.supports_double_threadsize ?
props->maxComputeWorkGroupInvocations = pdevice->info->props.supports_double_threadsize ?
pdevice->info->threadsize_base * 2 * pdevice->info->max_waves :
pdevice->info->threadsize_base * pdevice->info->max_waves;
if (pdevice->info->a6xx.is_a702) {
if (pdevice->info->props.is_a702) {
props->maxComputeWorkGroupSize[0] =
props->maxComputeWorkGroupSize[1] = 512;
props->maxComputeWorkGroupSize[2] = 64;
@ -1138,7 +1138,7 @@ tu_get_properties(struct tu_physical_device *pdevice,
props->subPixelInterpolationOffsetBits = 4;
props->maxFramebufferWidth = (1 << 14);
props->maxFramebufferHeight = (1 << 14);
props->maxFramebufferLayers = (1 << (pdevice->info->a6xx.is_a702 ? 8 : 10));
props->maxFramebufferLayers = (1 << (pdevice->info->props.is_a702 ? 8 : 10));
props->framebufferColorSampleCounts = sample_counts;
props->framebufferDepthSampleCounts = sample_counts;
props->framebufferStencilSampleCounts = sample_counts;
@ -1158,12 +1158,12 @@ tu_get_properties(struct tu_physical_device *pdevice,
props->discreteQueuePriorities = 2;
props->pointSizeRange[0] = 1;
props->pointSizeRange[1] = 4092;
props->lineWidthRange[0] = pdevice->info->a6xx.line_width_min;
props->lineWidthRange[1] = pdevice->info->a6xx.line_width_max;
props->lineWidthRange[0] = pdevice->info->props.line_width_min;
props->lineWidthRange[1] = pdevice->info->props.line_width_max;
props->pointSizeGranularity = 0.0625;
props->lineWidthGranularity =
pdevice->info->a6xx.line_width_max == 1.0 ? 0.0 : 0.5;
props->strictLines = !pdevice->info->a6xx.is_a702;
pdevice->info->props.line_width_max == 1.0 ? 0.0 : 0.5;
props->strictLines = !pdevice->info->props.is_a702;
props->standardSampleLocations = true;
props->optimalBufferCopyOffsetAlignment = 128;
props->optimalBufferCopyRowPitchAlignment = 128;
@ -1201,7 +1201,7 @@ tu_get_properties(struct tu_physical_device *pdevice,
props->meshAndTaskShaderDerivatives = false;
/* VK_KHR_fragment_shading_rate */
if (pdevice->info->a6xx.has_attachment_shading_rate) {
if (pdevice->info->props.has_attachment_shading_rate) {
props->minFragmentShadingRateAttachmentTexelSize = {8, 8};
props->maxFragmentShadingRateAttachmentTexelSize = {8, 8};
} else {
@ -1210,7 +1210,7 @@ tu_get_properties(struct tu_physical_device *pdevice,
}
props->maxFragmentShadingRateAttachmentTexelSizeAspectRatio = 1;
props->primitiveFragmentShadingRateWithMultipleViewports =
pdevice->info->a7xx.has_primitive_shading_rate;
pdevice->info->props.has_primitive_shading_rate;
/* A7XX TODO: dEQP-VK.fragment_shading_rate.*.srlayered.* are failing
* for some reason.
*/
@ -1232,7 +1232,7 @@ tu_get_properties(struct tu_physical_device *pdevice,
props->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
/* VK_EXT_transform_feedback */
if (pdevice->info->a6xx.is_a702) {
if (pdevice->info->props.is_a702) {
/* a702 only 32 streamout ram entries.. 1 stream, 64 components */
props->maxTransformFeedbackStreams = 1;
} else {
@ -1346,8 +1346,8 @@ tu_get_properties(struct tu_physical_device *pdevice,
props->uniformBufferDescriptorSize = A6XX_TEX_CONST_DWORDS * 4;
props->robustUniformBufferDescriptorSize = A6XX_TEX_CONST_DWORDS * 4;
props->storageBufferDescriptorSize = A6XX_TEX_CONST_DWORDS * 4 * (1 +
COND(pdevice->info->a6xx.storage_16bit && !pdevice->info->a6xx.has_isam_v, 1) +
COND(pdevice->info->a7xx.storage_8bit, 1));
COND(pdevice->info->props.storage_16bit && !pdevice->info->props.has_isam_v, 1) +
COND(pdevice->info->props.storage_8bit, 1));
props->robustStorageBufferDescriptorSize =
props->storageBufferDescriptorSize;
props->accelerationStructureDescriptorSize = 4 * A6XX_TEX_CONST_DWORDS;
@ -1543,7 +1543,7 @@ tu_physical_device_init(struct tu_physical_device *device,
/* Print a suffix if raytracing is disabled by the SW fuse, in an attempt
* to avoid confusion when apps don't work.
*/
bool raytracing_disabled = info.a7xx.has_sw_fuse &&
bool raytracing_disabled = info.props.has_sw_fuse &&
!device->has_raytracing;
const char *rt_suffix = raytracing_disabled ? " (raytracing disabled)" : "";
@ -1569,26 +1569,26 @@ tu_physical_device_init(struct tu_physical_device *device,
device->dev_info = info;
device->info = &device->dev_info;
uint32_t depth_cache_size =
device->info->num_ccu * device->info->a6xx.sysmem_per_ccu_depth_cache_size;
device->info->num_ccu * device->info->props.sysmem_per_ccu_depth_cache_size;
uint32_t color_cache_size =
(device->info->num_ccu *
device->info->a6xx.sysmem_per_ccu_color_cache_size);
device->info->props.sysmem_per_ccu_color_cache_size);
uint32_t color_cache_size_gmem =
color_cache_size /
(1 << device->info->a6xx.gmem_ccu_color_cache_fraction);
(1 << device->info->props.gmem_ccu_color_cache_fraction);
device->ccu_depth_offset_bypass = 0;
device->ccu_offset_bypass =
device->ccu_depth_offset_bypass + depth_cache_size;
if (device->info->a7xx.has_gmem_vpc_attr_buf) {
if (device->info->props.has_gmem_vpc_attr_buf) {
device->vpc_attr_buf_size_bypass =
device->info->a7xx.sysmem_vpc_attr_buf_size;
device->info->props.sysmem_vpc_attr_buf_size;
device->vpc_attr_buf_offset_bypass =
device->ccu_offset_bypass + color_cache_size;
device->vpc_attr_buf_size_gmem =
device->info->a7xx.gmem_vpc_attr_buf_size;
device->info->props.gmem_vpc_attr_buf_size;
device->vpc_attr_buf_offset_gmem =
device->gmem_size -
(device->vpc_attr_buf_size_gmem * device->info->num_ccu);
@ -1603,9 +1603,9 @@ tu_physical_device_init(struct tu_physical_device *device,
}
if (instance->reserve_descriptor_set) {
device->usable_sets = device->reserved_set_idx = device->info->a6xx.max_sets - 1;
device->usable_sets = device->reserved_set_idx = device->info->props.max_sets - 1;
} else {
device->usable_sets = device->info->a6xx.max_sets;
device->usable_sets = device->info->props.max_sets;
device->reserved_set_idx = -1;
}
break;
@ -2812,8 +2812,8 @@ tu_CreateDevice(VkPhysicalDevice physicalDevice,
.disable_cache = true,
.bindless_fb_read_descriptor = -1,
.bindless_fb_read_slot = -1,
.storage_16bit = physical_device->info->a6xx.storage_16bit,
.storage_8bit = physical_device->info->a7xx.storage_8bit,
.storage_16bit = physical_device->info->props.storage_16bit,
.storage_8bit = physical_device->info->props.storage_8bit,
.shared_push_consts = !TU_DEBUG(PUSH_CONSTS_PER_STAGE),
.uche_trap_base = physical_device->uche_trap_base,
};
@ -2971,7 +2971,7 @@ tu_CreateDevice(VkPhysicalDevice physicalDevice,
if (result != VK_SUCCESS)
goto fail_bin_preamble;
if (physical_device->info->a7xx.cmdbuf_start_a725_quirk) {
if (physical_device->info->props.cmdbuf_start_a725_quirk) {
result = tu_init_cmdbuf_start_a725_quirk(device);
if (result != VK_SUCCESS)
goto fail_a725_workaround;
@ -3009,7 +3009,7 @@ tu_CreateDevice(VkPhysicalDevice physicalDevice,
}
device->use_z24uint_s8uint =
physical_device->info->a6xx.has_z24uint_s8uint &&
physical_device->info->props.has_z24uint_s8uint &&
(!border_color_without_format ||
physical_device->instance->disable_d24s8_border_color_workaround);
device->use_lrz = !TU_DEBUG_START(NOLRZ);

6
src/freedreno/vulkan/tu_formats.cc
View file

@ -101,7 +101,7 @@ static bool
tu_format_linear_filtering_supported(struct tu_physical_device *physical_device,
VkFormat vk_format)
{
if (physical_device->info->a6xx.is_a702) {
if (physical_device->info->props.is_a702) {
switch (vk_format) {
case VK_FORMAT_D16_UNORM:
case VK_FORMAT_D24_UNORM_S8_UINT:
@ -184,7 +184,7 @@ tu_physical_device_get_format_properties(
if (ycbcr_info->n_planes > 1) {
optimal |= VK_FORMAT_FEATURE_2_COSITED_CHROMA_SAMPLES_BIT |
VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_YCBCR_CONVERSION_LINEAR_FILTER_BIT;
if (physical_device->info->a6xx.has_separate_chroma_filter)
if (physical_device->info->props.has_separate_chroma_filter)
optimal |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_YCBCR_CONVERSION_SEPARATE_RECONSTRUCTION_FILTER_BIT;
}
} else {
@ -807,7 +807,7 @@ tu_GetPhysicalDeviceImageFormatProperties2(
(base_info->usage & ~VK_IMAGE_USAGE_HOST_TRANSFER_BIT_EXT),
(base_info->usage & ~VK_IMAGE_USAGE_HOST_TRANSFER_BIT_EXT),
physical_device->info, VK_SAMPLE_COUNT_1_BIT, 1,
physical_device->info->a6xx.has_z24uint_s8uint));
physical_device->info->props.has_z24uint_s8uint));
}
return VK_SUCCESS;

14
src/freedreno/vulkan/tu_image.cc
View file

@ -332,7 +332,7 @@ ubwc_possible(struct tu_device *device,
bool use_z24uint_s8uint)
{
/* TODO: enable for a702 */
if (info->a6xx.is_a702)
if (info->props.is_a702)
return false;
/* UBWC isn't possible with sparse residency, because unbound blocks may
@ -355,10 +355,10 @@ ubwc_possible(struct tu_device *device,
* all 1's prior to a740. Disable UBWC for snorm.
*/
if (vk_format_is_snorm(format) &&
!info->a7xx.ubwc_unorm_snorm_int_compatible)
!info->props.ubwc_unorm_snorm_int_compatible)
return false;
if (!info->a6xx.has_8bpp_ubwc &&
if (!info->props.has_8bpp_ubwc &&
vk_format_get_blocksizebits(format) == 8 &&
vk_format_get_plane_count(format) == 1)
return false;
@ -382,7 +382,7 @@ ubwc_possible(struct tu_device *device,
* and we can't change the descriptor so we can't do this.
*/
if (((usage | stencil_usage) & VK_IMAGE_USAGE_STORAGE_BIT) &&
!info->a7xx.supports_uav_ubwc) {
!info->props.supports_uav_ubwc) {
return false;
}
@ -391,7 +391,7 @@ ubwc_possible(struct tu_device *device,
* ordinary draw calls writing read/depth. WSL blob seem to use ubwc
* sometimes for depth/stencil.
*/
if (info->a6xx.broken_ds_ubwc_quirk &&
if (info->props.broken_ds_ubwc_quirk &&
vk_format_is_depth_or_stencil(format))
return false;
@ -416,7 +416,7 @@ ubwc_possible(struct tu_device *device,
(stencil_usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)))
return false;
if (!info->a6xx.has_z24uint_s8uint &&
if (!info->props.has_z24uint_s8uint &&
(format == VK_FORMAT_D24_UNORM_S8_UINT ||
format == VK_FORMAT_X8_D24_UNORM_PACK32) &&
samples > VK_SAMPLE_COUNT_1_BIT) {
@ -727,7 +727,7 @@ tu_image_init(struct tu_device *device, struct tu_image *image,
vk_find_struct_const(pCreateInfo->pNext, IMAGE_FORMAT_LIST_CREATE_INFO);
if (!tu6_mutable_format_list_ubwc_compatible(device->physical_device->info,
fmt_list)) {
bool mutable_ubwc_fc = device->physical_device->info->a7xx.ubwc_all_formats_compatible;
bool mutable_ubwc_fc = device->physical_device->info->props.ubwc_all_formats_compatible;
/* NV12 uses a special compression scheme for the Y channel which
* doesn't support reinterpretation. We have to fall back to linear

20
src/freedreno/vulkan/tu_lrz.cc
View file

@ -149,7 +149,7 @@ static void
tu6_write_lrz_reg(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
struct tu_reg_value reg)
{
if (cmd->device->physical_device->info->a6xx.lrz_track_quirk) {
if (cmd->device->physical_device->info->props.lrz_track_quirk) {
tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_LRZ));
tu_cs_emit(cs, reg.reg);
@ -214,7 +214,7 @@ tu_lrz_init_state(struct tu_cmd_buffer *cmd,
bool clears_depth = att->clear_mask &
(VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_DEPTH_BIT);
bool has_gpu_tracking =
cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking;
cmd->device->physical_device->info->props.has_lrz_dir_tracking;
if (!has_gpu_tracking && !clears_depth)
return;
@ -265,7 +265,7 @@ tu_lrz_init_secondary(struct tu_cmd_buffer *cmd,
const struct tu_render_pass_attachment *att)
{
bool has_gpu_tracking =
cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking;
cmd->device->physical_device->info->props.has_lrz_dir_tracking;
if (!has_gpu_tracking)
return;
@ -356,7 +356,7 @@ tu_lrz_begin_renderpass(struct tu_cmd_buffer *cmd)
lrz_img_count++;
}
if (cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking &&
if (cmd->device->physical_device->info->props.has_lrz_dir_tracking &&
cmd->state.pass->subpass_count > 1 && lrz_img_count > 1) {
/* Theoretically we could switch between LRZ buffers during the binning
* and tiling passes, but it is untested and would add complexity for
@ -802,7 +802,7 @@ template <chip CHIP>
void
tu_lrz_sysmem_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
if (cmd->device->physical_device->info->a6xx.has_lrz_feedback) {
if (cmd->device->physical_device->info->props.has_lrz_feedback) {
tu_lrz_tiling_begin<CHIP>(cmd, cs);
return;
}
@ -816,7 +816,7 @@ tu_lrz_sysmem_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
struct tu_lrz_state *lrz = &cmd->state.lrz;
if (cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking) {
if (cmd->device->physical_device->info->props.has_lrz_dir_tracking) {
tu_disable_lrz<CHIP>(cmd, cs, lrz->image_view->image);
/* Make sure depth view comparison will fail. */
tu6_write_lrz_reg(cmd, cs,
@ -847,7 +847,7 @@ template <chip CHIP>
void
tu_lrz_sysmem_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
if (cmd->device->physical_device->info->a6xx.has_lrz_feedback) {
if (cmd->device->physical_device->info->props.has_lrz_feedback) {
tu_lrz_tiling_end<CHIP>(cmd, cs);
return;
}
@ -862,7 +862,7 @@ void
tu_disable_lrz(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
struct tu_image *image)
{
if (!cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking)
if (!cmd->device->physical_device->info->props.has_lrz_dir_tracking)
return;
if (!image->lrz_layout.lrz_total_size)
@ -921,7 +921,7 @@ template <chip CHIP>
void
tu_disable_lrz_cpu(struct tu_device *device, struct tu_image *image)
{
if (!device->physical_device->info->a6xx.has_lrz_dir_tracking)
if (!device->physical_device->info->props.has_lrz_dir_tracking)
return;
if (!image->lrz_layout.lrz_total_size)
@ -970,7 +970,7 @@ tu_lrz_clear_depth_image(struct tu_cmd_buffer *cmd,
const VkImageSubresourceRange *pRanges)
{
if (!rangeCount || !image->lrz_layout.lrz_total_size ||
!cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking)
!cmd->device->physical_device->info->props.has_lrz_dir_tracking)
return;
/* We cannot predict which depth subresource would be used later on,

4
src/freedreno/vulkan/tu_nir_lower_multiview.cc
View file

@ -76,7 +76,7 @@ tu_nir_lower_multiview(nir_shader *nir, uint32_t mask, struct tu_device *dev)
.allowed_per_view_outputs = VARYING_BIT_POS
};
if (!dev->physical_device->info->a6xx.supports_multiview_mask)
if (!dev->physical_device->info->props.supports_multiview_mask)
NIR_PASS(progress, nir, lower_multiview_mask, &options.view_mask);
unsigned num_views = util_logbase2(mask) + 1;
@ -86,7 +86,7 @@ tu_nir_lower_multiview(nir_shader *nir, uint32_t mask, struct tu_device *dev)
* tests pass on a640/a650 and fail on a630.
*/
unsigned max_views_for_multipos =
dev->physical_device->info->a6xx.supports_multiview_mask ? 16 : 10;
dev->physical_device->info->props.supports_multiview_mask ? 16 : 10;
/* Speculatively assign output locations so that we know num_outputs. We
* will assign output locations for real after this pass.

2
src/freedreno/vulkan/tu_pass.cc
View file

@ -571,7 +571,7 @@ tu_render_pass_cond_config(struct tu_device *device,
/* With generic clears CmdClearAttachments isn't a draw and doesn't
* contribute to bin's geometry.
*/
if (device->physical_device->info->a7xx.has_generic_clear)
if (device->physical_device->info->props.has_generic_clear)
return;
for (uint32_t i = 0; i < pass->attachment_count; i++) {

32
src/freedreno/vulkan/tu_pipeline.cc
View file

@ -418,7 +418,7 @@ tu6_emit_dynamic_offset(struct tu_cs *cs,
if (!xs)
return;
if (cs->device->physical_device->info->a7xx.load_shader_consts_via_preamble) {
if (cs->device->physical_device->info->props.load_shader_consts_via_preamble) {
if (shader->const_state.dynamic_offsets_ubo.size == 0)
return;
@ -494,7 +494,7 @@ tu6_setup_streamout(struct tu_cs *cs,
#define A6XX_SO_PROG_DWORDS 64
uint32_t prog[A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS] = {};
BITSET_DECLARE(valid_dwords, A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS) = {0};
bool has_pc_dgen_so_cntl = cs->device->physical_device->info->a6xx.has_pc_dgen_so_cntl;
bool has_pc_dgen_so_cntl = cs->device->physical_device->info->props.has_pc_dgen_so_cntl;
/* TODO: streamout state should be in a non-GMEM draw state */
@ -617,7 +617,7 @@ tu6_emit_const(struct tu_cs *cs, uint32_t opcode, enum tu_geom_consts_type type,
assert(size % 4 == 0);
dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
if (!cs->device->physical_device->info->a7xx.load_shader_consts_via_preamble) {
if (!cs->device->physical_device->info->props.load_shader_consts_via_preamble) {
uint32_t base;
switch (type) {
case TU_CONSTS_PRIMITIVE_MAP:
@ -967,7 +967,7 @@ tu6_emit_vpc(struct tu_cs *cs,
* an input primitive type with adjacency, an output primitive type of
* points, and a high enough vertex count causes a hang.
*/
if (cs->device->physical_device->info->a7xx.gs_vpc_adjacency_quirk &&
if (cs->device->physical_device->info->props.gs_vpc_adjacency_quirk &&
gs && gs->gs.output_primitive == MESA_PRIM_POINTS &&
linkage.max_loc > 4) {
linkage.max_loc = MAX2(linkage.max_loc, 9);
@ -1121,7 +1121,7 @@ tu6_patch_control_points_size(struct tu_device *dev,
const struct tu_program_state *program,
uint32_t patch_control_points)
{
if (dev->physical_device->info->a7xx.load_shader_consts_via_preamble) {
if (dev->physical_device->info->props.load_shader_consts_via_preamble) {
#define EMIT_CONST_DWORDS(const_dwords) (6 + const_dwords + 4)
return EMIT_CONST_DWORDS(4) +
EMIT_CONST_DWORDS(HS_PARAMS_SIZE) + 2 + 2 + 2;
@ -1186,7 +1186,7 @@ tu6_emit_patch_control_points(struct tu_cs *cs,
const uint32_t vs_hs_local_mem_size = 16384;
uint32_t max_patches_per_wave;
if (dev->physical_device->info->a6xx.tess_use_shared) {
if (dev->physical_device->info->props.tess_use_shared) {
/* HS invocations for a patch are always within the same wave,
* making barriers less expensive. VS can't have barriers so we
* don't care about VS invocations being in the same wave.
@ -2340,7 +2340,7 @@ tu_emit_program_state(struct tu_cs *sub_cs,
prog->per_view_viewport =
!last_variant->writes_viewport &&
shaders[MESA_SHADER_FRAGMENT]->fs.has_fdm &&
dev->physical_device->info->a6xx.has_per_view_viewport;
dev->physical_device->info->props.has_per_view_viewport;
prog->per_layer_viewport = last_shader->per_layer_viewport;
prog->fake_single_viewport = prog->per_view_viewport ||
prog->per_layer_viewport;
@ -3280,10 +3280,10 @@ tu6_rast_size(struct tu_device *dev,
bool per_view_viewport,
bool disable_fs)
{
if (CHIP == A6XX && dev->physical_device->info->a6xx.is_a702) {
if (CHIP == A6XX && dev->physical_device->info->props.is_a702) {
return 17;
} else if (CHIP == A6XX) {
return 15 + (dev->physical_device->info->a6xx.has_legacy_pipeline_shading_rate ? 8 : 0);
return 15 + (dev->physical_device->info->props.has_legacy_pipeline_shading_rate ? 8 : 0);
} else {
return 27;
}
@ -3332,7 +3332,7 @@ tu6_emit_rast(struct tu_cs *cs,
tu_cs_emit_regs(cs,
PC_DGEN_RAST_CNTL(CHIP, polygon_mode));
if (CHIP == A7XX || cs->device->physical_device->info->a6xx.is_a702) {
if (CHIP == A7XX || cs->device->physical_device->info->props.is_a702) {
tu_cs_emit_regs(cs,
A6XX_VPC_PS_RAST_CNTL(polygon_mode));
}
@ -3395,7 +3395,7 @@ tu6_emit_rast(struct tu_cs *cs,
A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
A6XX_GRAS_SU_POINT_SIZE(1.0f));
if (CHIP == A6XX && cs->device->physical_device->info->a6xx.has_legacy_pipeline_shading_rate) {
if (CHIP == A6XX && cs->device->physical_device->info->props.has_legacy_pipeline_shading_rate) {
tu_cs_emit_regs(cs, A6XX_RB_UNKNOWN_8A00());
tu_cs_emit_regs(cs, A6XX_RB_UNKNOWN_8A10());
tu_cs_emit_regs(cs, A6XX_RB_UNKNOWN_8A20());
@ -3511,7 +3511,7 @@ tu6_emit_rb_depth_cntl(struct tu_cs *cs,
*/
if (ds->depth.bounds_test.enable &&
!ds->depth.test_enable &&
cs->device->physical_device->info->a6xx.depth_bounds_require_depth_test_quirk) {
cs->device->physical_device->info->props.depth_bounds_require_depth_test_quirk) {
depth_test = true;
zfunc = FUNC_ALWAYS;
}
@ -3847,7 +3847,7 @@ tu_pipeline_builder_emit_state(struct tu_pipeline_builder *builder,
(lib->state &
VK_GRAPHICS_PIPELINE_LIBRARY_FRAGMENT_OUTPUT_INTERFACE_BIT_EXT);
}
if (!builder->device->physical_device->info->a6xx.has_coherent_ubwc_flag_caches) {
if (!builder->device->physical_device->info->props.has_coherent_ubwc_flag_caches) {
DRAW_STATE_COND(prim_mode_sysmem,
TU_DYNAMIC_STATE_PRIM_MODE_SYSMEM,
has_raster_order_state,
@ -3858,7 +3858,7 @@ tu_pipeline_builder_emit_state(struct tu_pipeline_builder *builder,
&pipeline->prim_order.sysmem_single_prim_mode);
}
if (builder->device->physical_device->info->a6xx.has_attachment_shading_rate) {
if (builder->device->physical_device->info->props.has_attachment_shading_rate) {
bool has_fsr_att =
builder->graphics_state.pipeline_flags &
VK_PIPELINE_CREATE_2_RENDERING_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR;
@ -4054,7 +4054,7 @@ tu_emit_draw_state(struct tu_cmd_buffer *cmd)
DRAW_STATE(blend_constants, VK_DYNAMIC_STATE_BLEND_CONSTANTS,
&cmd->vk.dynamic_graphics_state.cb);
if (cmd->device->physical_device->info->a6xx.has_attachment_shading_rate) {
if (cmd->device->physical_device->info->props.has_attachment_shading_rate) {
DRAW_STATE_COND(fragment_shading_rate,
TU_DYNAMIC_STATE_A7XX_FRAGMENT_SHADING_RATE,
cmd->state.dirty & (TU_CMD_DIRTY_SUBPASS | TU_CMD_DIRTY_SHADING_RATE),
@ -4089,7 +4089,7 @@ tu_emit_draw_state(struct tu_cmd_buffer *cmd)
cmd->state.shaders[MESA_SHADER_TESS_EVAL],
&cmd->state.program,
cmd->vk.dynamic_graphics_state.ts.patch_control_points);
if (!cmd->device->physical_device->info->a6xx.has_coherent_ubwc_flag_caches) {
if (!cmd->device->physical_device->info->props.has_coherent_ubwc_flag_caches) {
DRAW_STATE_COND(prim_mode_sysmem,
TU_DYNAMIC_STATE_PRIM_MODE_SYSMEM,
cmd->state.dirty & (TU_CMD_DIRTY_RAST_ORDER |

12
src/freedreno/vulkan/tu_query_pool.cc
View file

@ -1045,7 +1045,7 @@ emit_begin_occlusion_query(struct tu_cmd_buffer *cmdbuf,
tu_cs_emit_regs(cs,
A6XX_RB_SAMPLE_COUNTER_CNTL(.copy = true));
if (!cmdbuf->device->physical_device->info->a7xx.has_event_write_sample_count) {
if (!cmdbuf->device->physical_device->info->props.has_event_write_sample_count) {
tu_cs_emit_regs(cs,
A6XX_RB_SAMPLE_COUNTER_BASE(.qword = begin_iova));
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
@ -1178,7 +1178,7 @@ emit_begin_perf_query_raw(struct tu_cmd_buffer *cmdbuf,
struct tu_perf_query_raw *perf_query = &pool->perf_query.raw;
uint32_t last_pass = ~0;
bool has_pred_bit =
cmdbuf->device->physical_device->info->a6xx.has_pred_bit;
cmdbuf->device->physical_device->info->props.has_pred_bit;
if (cmdbuf->state.pass && !has_pred_bit) {
cmdbuf->state.rp.draw_cs_writes_to_cond_pred = true;
@ -1457,7 +1457,7 @@ emit_end_occlusion_query(struct tu_cmd_buffer *cmdbuf,
uint64_t result_iova = occlusion_query_iova(pool, query, result);
uint64_t end_iova = occlusion_query_iova(pool, query, end);
if (!cmdbuf->device->physical_device->info->a7xx.has_event_write_sample_count) {
if (!cmdbuf->device->physical_device->info->props.has_event_write_sample_count) {
tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 4);
tu_cs_emit_qw(cs, end_iova);
tu_cs_emit_qw(cs, 0xffffffffffffffffull);
@ -1468,7 +1468,7 @@ emit_end_occlusion_query(struct tu_cmd_buffer *cmdbuf,
tu_cs_emit_regs(cs,
A6XX_RB_SAMPLE_COUNTER_CNTL(.copy = true));
if (!cmdbuf->device->physical_device->info->a7xx.has_event_write_sample_count) {
if (!cmdbuf->device->physical_device->info->props.has_event_write_sample_count) {
tu_cs_emit_regs(cs,
A6XX_RB_SAMPLE_COUNTER_BASE(.qword = end_iova));
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
@ -1520,7 +1520,7 @@ emit_end_occlusion_query(struct tu_cmd_buffer *cmdbuf,
tu_cs_emit_wfi(cs);
if (cmdbuf->device->physical_device->info->a7xx.has_generic_clear) {
if (cmdbuf->device->physical_device->info->props.has_generic_clear) {
/* If the next renderpass uses the same depth attachment, clears it
* with generic clear - ZPASS_DONE may somehow read stale values that
* are apparently invalidated by CCU_INVALIDATE_DEPTH.
@ -1679,7 +1679,7 @@ emit_end_perf_query_raw(struct tu_cmd_buffer *cmdbuf,
uint64_t result_iova;
uint32_t last_pass = ~0;
bool has_pred_bit =
cmdbuf->device->physical_device->info->a6xx.has_pred_bit;
cmdbuf->device->physical_device->info->props.has_pred_bit;
/* Wait for the profiled work to finish so that collected counter values
* are as accurate as possible.

36
src/freedreno/vulkan/tu_shader.cc
View file

@ -465,7 +465,7 @@ lower_ssbo_ubo_intrinsic(struct tu_device *dev,
}
nir_def *base_idx = nir_mov_scalar(b, scalar_idx);
for (unsigned i = 0; i < dev->physical_device->info->a6xx.max_sets; i++) {
for (unsigned i = 0; i < dev->physical_device->info->props.max_sets; i++) {
/* if (base_idx == i) { ... */
nir_if *nif = nir_push_if(b, nir_ieq_imm(b, base_idx, i));
@ -503,7 +503,7 @@ lower_ssbo_ubo_intrinsic(struct tu_device *dev,
nir_def *result =
nir_undef(b, intrin->def.num_components, intrin->def.bit_size);
for (int i = dev->physical_device->info->a6xx.max_sets - 1; i >= 0; i--) {
for (int i = dev->physical_device->info->props.max_sets - 1; i >= 0; i--) {
nir_pop_if(b, NULL);
if (info->has_dest)
result = nir_if_phi(b, results[i], result);
@ -844,7 +844,7 @@ lower_inline_ubo(nir_builder *b, nir_intrinsic_instr *intrin, void *cb_data)
unsigned range;
bool use_load = false;
bool use_ldg_k =
params->dev->physical_device->info->a7xx.load_inline_uniforms_via_preamble_ldgk;
params->dev->physical_device->info->props.load_inline_uniforms_via_preamble_ldgk;
for (unsigned i = 0; i < const_state->num_inline_ubos; i++) {
if (const_state->ubos[i].base == binding.desc_set &&
@ -1060,7 +1060,7 @@ tu_lower_io(nir_shader *shader, struct tu_device *dev,
*/
size_t ldgk_consts = 0;
bool use_ldg_k =
dev->physical_device->info->a7xx.load_inline_uniforms_via_preamble_ldgk;
dev->physical_device->info->props.load_inline_uniforms_via_preamble_ldgk;
for (unsigned set = 0; set < layout->num_sets; set++) {
const struct tu_descriptor_set_layout *desc_layout =
layout->set[set].layout;
@ -1243,12 +1243,12 @@ lower_ssbo_descriptor_instr(nir_builder *b, nir_intrinsic_instr *intrin,
* - 8-bit SSBO loads and stores -- next-index descriptor is dedicated to
* storage accesses of that size.
*/
if ((dev->physical_device->info->a6xx.storage_16bit &&
!dev->physical_device->info->a6xx.has_isam_v &&
if ((dev->physical_device->info->props.storage_16bit &&
!dev->physical_device->info->props.has_isam_v &&
intrin->intrinsic == nir_intrinsic_load_ssbo &&
(nir_intrinsic_access(intrin) & ACCESS_CAN_REORDER) &&
intrin->def.bit_size > 16) ||
(dev->physical_device->info->a7xx.storage_8bit &&
(dev->physical_device->info->props.storage_8bit &&
((intrin->intrinsic == nir_intrinsic_load_ssbo && intrin->def.bit_size == 8) ||
(intrin->intrinsic == nir_intrinsic_store_ssbo && intrin->src[0].ssa->bit_size == 8)))) {
unsigned buffer_src;
@ -1594,7 +1594,7 @@ tu6_emit_xs(struct tu_cs *cs,
));
break;
case MESA_SHADER_COMPUTE:
thrsz = cs->device->physical_device->info->a6xx
thrsz = cs->device->physical_device->info->props
.supports_double_threadsize ? thrsz : THREAD128;
tu_cs_emit_regs(cs, A6XX_SP_CS_CNTL_0(
.halfregfootprint = xs->info.max_half_reg + 1,
@ -1638,7 +1638,7 @@ tu6_emit_xs(struct tu_cs *cs,
if (cs->device->physical_device->info->chip == A6XX) {
uint32_t shader_preload_size =
MIN2(xs->instrlen, cs->device->physical_device->info->a6xx.instr_cache_size);
MIN2(xs->instrlen, cs->device->physical_device->info->props.instr_cache_size);
tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3);
tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
@ -1657,7 +1657,7 @@ tu6_emit_xs(struct tu_cs *cs,
unsigned immediate_size = tu_xs_get_immediates_packet_size_dwords(xs);
if (immediate_size > 0) {
assert(!cs->device->physical_device->info->a7xx.load_shader_consts_via_preamble);
assert(!cs->device->physical_device->info->props.load_shader_consts_via_preamble);
tu_cs_emit_pkt7(cs, tu6_stage2opcode(stage), 3 + immediate_size);
tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
@ -1761,7 +1761,7 @@ tu6_emit_cs_config(struct tu_cs *cs,
tu_cs_emit(cs, A6XX_SP_CS_CNTL_1_SHARED_SIZE(shared_size) |
A6XX_SP_CS_CNTL_1_CONSTANTRAMMODE(mode));
if (CHIP == A6XX && cs->device->physical_device->info->a6xx.has_lpac) {
if (CHIP == A6XX && cs->device->physical_device->info->props.has_lpac) {
tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CTRL_REG1, 1);
tu_cs_emit(cs, A6XX_HLSQ_CS_CTRL_REG1_SHARED_SIZE(shared_size) |
A6XX_HLSQ_CS_CTRL_REG1_CONSTANTRAMMODE(mode));
@ -1778,7 +1778,7 @@ tu6_emit_cs_config(struct tu_cs *cs,
* which is always set to THREAD128.
*/
enum a6xx_threadsize thrsz = v->info.double_threadsize ? THREAD128 : THREAD64;
enum a6xx_threadsize thrsz_cs = cs->device->physical_device->info->a6xx
enum a6xx_threadsize thrsz_cs = cs->device->physical_device->info->props
.supports_double_threadsize ? thrsz : THREAD128;
if (CHIP == A6XX) {
tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONST_CONFIG_0, 2);
@ -1789,12 +1789,12 @@ tu6_emit_cs_config(struct tu_cs *cs,
A6XX_SP_CS_CONST_CONFIG_0_LOCALIDREGID(local_invocation_id));
tu_cs_emit(cs, A6XX_SP_CS_WGE_CNTL_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_SP_CS_WGE_CNTL_THREADSIZE(thrsz_cs));
if (!cs->device->physical_device->info->a6xx.supports_double_threadsize) {
if (!cs->device->physical_device->info->props.supports_double_threadsize) {
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_WAVE_CNTL, 1);
tu_cs_emit(cs, A6XX_SP_PS_WAVE_CNTL_THREADSIZE(thrsz));
}
if (cs->device->physical_device->info->a6xx.has_lpac) {
if (cs->device->physical_device->info->props.has_lpac) {
tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_WIE_CNTL_0, 2);
tu_cs_emit(cs,
A6XX_SP_CS_WIE_CNTL_0_WGIDCONSTID(work_group_id) |
@ -1949,7 +1949,7 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
tu_cs_emit_regs(cs,
SP_LB_PARAM_LIMIT(CHIP,
.primallocthreshold =
cs->device->physical_device->info->a6xx.prim_alloc_threshold),
cs->device->physical_device->info->props.prim_alloc_threshold),
SP_REG_PROG_ID_0(CHIP, .faceregid = face_regid,
.sampleid = samp_id_regid,
.samplemask = smask_in_regid,
@ -2186,7 +2186,7 @@ tu6_emit_vs(struct tu_cs *cs,
* CP_EVENT_WRITE when multiview is disabled. I'm not exactly sure what
* this is working around yet.
*/
if (cs->device->physical_device->info->a6xx.has_cp_reg_write) {
if (cs->device->physical_device->info->props.has_cp_reg_write) {
tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(UNK_EVENT_WRITE));
tu_cs_emit(cs, REG_A6XX_PC_STEREO_RENDERING_CNTL);
@ -2199,7 +2199,7 @@ tu6_emit_vs(struct tu_cs *cs,
tu_cs_emit(cs, multiview_cntl);
if (multiview_cntl &&
cs->device->physical_device->info->a6xx.supports_multiview_mask) {
cs->device->physical_device->info->props.supports_multiview_mask) {
tu_cs_emit_pkt4(cs, REG_A6XX_PC_STEREO_RENDERING_VIEWMASK, 1);
tu_cs_emit(cs, view_mask);
}
@ -3324,7 +3324,7 @@ tu_shader_key_subgroup_size(struct tu_shader_key *key,
struct tu_device *dev)
{
enum ir3_wavesize_option api_wavesize, real_wavesize;
if (!dev->physical_device->info->a6xx.supports_double_threadsize) {
if (!dev->physical_device->info->props.supports_double_threadsize) {
api_wavesize = IR3_SINGLE_ONLY;
real_wavesize = IR3_SINGLE_ONLY;
} else {

2
src/freedreno/vulkan/tu_util.cc
View file

@ -379,7 +379,7 @@ tu_tiling_config_update_pipe_layout(struct tu_vsc_config *vsc,
* area can prevent bin merging from happening. Maximize the size of each
* pipe instead of minimizing it.
*/
if (fdm && dev->physical_device->info->a6xx.has_bin_mask &&
if (fdm && dev->physical_device->info->props.has_bin_mask &&
!TU_DEBUG(NO_BIN_MERGING)) {
vsc->pipe0.width = 4;
vsc->pipe0.height = 8;

2
src/gallium/drivers/freedreno/a6xx/fd6_barrier.cc
View file

@ -138,7 +138,7 @@ fd6_memory_barrier(struct pipe_context *pctx, unsigned flags)
* with these opcodes, but the alternative would add unnecessary WAIT_FOR_ME's
* before draw opcodes that don't need it.
*/
if (fd_context(pctx)->screen->info->a6xx.indirect_draw_wfm_quirk) {
if (fd_context(pctx)->screen->info->props.indirect_draw_wfm_quirk) {
flushes |= FD6_WAIT_FOR_ME;
}
}

10
src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc
View file

@ -279,19 +279,19 @@ emit_blit_fini(struct fd_context *ctx, fd_cs &cs)
fd6_event_write<CHIP>(ctx, cs, FD_LABEL);
if (info->a6xx.magic.RB_DBG_ECO_CNTL != info->a6xx.magic.RB_DBG_ECO_CNTL_blit) {
if (info->props.magic.RB_DBG_ECO_CNTL != info->props.magic.RB_DBG_ECO_CNTL_blit) {
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd_pkt4(cs, 1)
.add(A6XX_RB_DBG_ECO_CNTL(.dword = info->a6xx.magic.RB_DBG_ECO_CNTL_blit));
.add(A6XX_RB_DBG_ECO_CNTL(.dword = info->props.magic.RB_DBG_ECO_CNTL_blit));
}
fd_pkt7(cs, CP_BLIT, 1)
.add(CP_BLIT_0(.op = BLIT_OP_SCALE));
if (info->a6xx.magic.RB_DBG_ECO_CNTL != info->a6xx.magic.RB_DBG_ECO_CNTL_blit) {
if (info->props.magic.RB_DBG_ECO_CNTL != info->props.magic.RB_DBG_ECO_CNTL_blit) {
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd_pkt4(cs, 1)
.add(A6XX_RB_DBG_ECO_CNTL(.dword = info->a6xx.magic.RB_DBG_ECO_CNTL));
.add(A6XX_RB_DBG_ECO_CNTL(.dword = info->props.magic.RB_DBG_ECO_CNTL));
}
}
@ -1414,7 +1414,7 @@ handle_zs_blit(struct fd_context *ctx,
/* non-UBWC Z24_UNORM_S8_UINT_AS_R8G8B8A8 is broken on a630, fall back to
* 8888_unorm.
*/
if (!ctx->screen->info->a6xx.has_z24uint_s8uint) {
if (!ctx->screen->info->props.has_z24uint_s8uint) {
if (!src->layout.ubwc && !dst->layout.ubwc) {
blit.src.format = PIPE_FORMAT_RGBA8888_UINT;
blit.dst.format = PIPE_FORMAT_RGBA8888_UINT;

16
src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
View file

@ -35,7 +35,7 @@ cs_program_emit_local_size(struct fd_context *ctx, fd_crb &crb,
* which is always set to THREAD128.
*/
enum a6xx_threadsize thrsz = v->info.double_threadsize ? THREAD128 : THREAD64;
enum a6xx_threadsize thrsz_cs = ctx->screen->info->a6xx
enum a6xx_threadsize thrsz_cs = ctx->screen->info->props
.supports_double_threadsize ? thrsz : THREAD128;
if (CHIP == A7XX) {
@ -98,7 +98,7 @@ cs_program_emit(struct fd_context *ctx, fd_crb &crb, struct ir3_shader_variant *
* which is always set to THREAD128.
*/
enum a6xx_threadsize thrsz = v->info.double_threadsize ? THREAD128 : THREAD64;
enum a6xx_threadsize thrsz_cs = ctx->screen->info->a6xx
enum a6xx_threadsize thrsz_cs = ctx->screen->info->props
.supports_double_threadsize ? thrsz : THREAD128;
if (CHIP == A6XX) {
@ -113,11 +113,11 @@ cs_program_emit(struct fd_context *ctx, fd_crb &crb, struct ir3_shader_variant *
.threadsize = thrsz_cs,
));
if (!ctx->screen->info->a6xx.supports_double_threadsize) {
if (!ctx->screen->info->props.supports_double_threadsize) {
crb.add(SP_PS_WAVE_CNTL(CHIP, .threadsize = thrsz));
}
if (ctx->screen->info->a6xx.has_lpac) {
if (ctx->screen->info->props.has_lpac) {
crb.add(A6XX_SP_CS_WIE_CNTL_0(
.wgidconstid = work_group_id,
.wgsizeconstid = INVALID_REG,
@ -181,7 +181,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
fd6_barrier_flush<CHIP>(cs, ctx->batch);
bool emit_instrlen_workaround =
cp->v->instrlen > ctx->screen->info->a6xx.instr_cache_size;
cp->v->instrlen > ctx->screen->info->props.instr_cache_size;
/* There appears to be a HW bug where in some rare circumstances it appears
* to accidentally use the FS instrlen instead of the CS instrlen, which
@ -234,7 +234,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
.constantrammode = mode,
));
if (CHIP == A6XX && ctx->screen->info->a6xx.has_lpac) {
if (CHIP == A6XX && ctx->screen->info->props.has_lpac) {
crb.add(HLSQ_CS_CTRL_REG1(CHIP,
.shared_size = shared_size,
.constantrammode = mode,
@ -328,14 +328,14 @@ fd6_get_compute_state_info(struct pipe_context *pctx, void *cso, struct pipe_com
cinfo->simd_sizes = threadsize_base;
cinfo->preferred_simd_size = threadsize_base;
if (info->a6xx.supports_double_threadsize && v->info.double_threadsize) {
if (info->props.supports_double_threadsize && v->info.double_threadsize) {
cinfo->max_threads *= 2;
cinfo->simd_sizes |= (threadsize_base * 2);
cinfo->preferred_simd_size *= 2;
}
unsigned reg_file_size_vec4 = info->a6xx.reg_size_vec4 * threadsize_base * info->wave_granularity;
unsigned reg_file_size_vec4 = info->props.reg_size_vec4 * threadsize_base * info->wave_granularity;
unsigned vec4_regs_per_thread = MAX2(v->info.max_reg + 1, 1);
cinfo->max_threads = MIN2(cinfo->max_threads, reg_file_size_vec4 / vec4_regs_per_thread);

10
src/gallium/drivers/freedreno/a6xx/fd6_const.cc
View file

@ -44,7 +44,7 @@ fd6_upload_emit_driver_ubo(struct fd_context *ctx, fd_cs &cs,
{
struct pipe_context *pctx = &ctx->base;
assert(ctx->screen->info->chip >= 7 && ctx->screen->info->a7xx.load_shader_consts_via_preamble);
assert(ctx->screen->info->chip >= 7 && ctx->screen->info->props.load_shader_consts_via_preamble);
if (!sizedwords || (base < 0))
return;
@ -162,7 +162,7 @@ emit_stage_tess_consts(fd_cs &cs, const struct ir3_shader_variant *v,
{
const struct ir3_const_state *const_state = ir3_const_state(v);
if (CHIP == A7XX && ctx->screen->info->a7xx.load_shader_consts_via_preamble) {
if (CHIP == A7XX && ctx->screen->info->props.load_shader_consts_via_preamble) {
int base = const_state->primitive_param_ubo.idx;
fd6_upload_emit_driver_ubo(ctx, cs, v, base, num_params, params);
@ -371,7 +371,7 @@ emit_driver_params(const struct ir3_shader_variant *v, fd_cs &dpconstobj,
const struct pipe_draw_indirect_info *indirect,
const struct ir3_driver_params_vs *vertex_params)
{
if (CHIP == A7XX && ctx->screen->info->a7xx.load_shader_consts_via_preamble) {
if (CHIP == A7XX && ctx->screen->info->props.load_shader_consts_via_preamble) {
const struct ir3_const_state *const_state = ir3_const_state(v);
int base = const_state->driver_params_ubo.idx;
@ -388,7 +388,7 @@ static inline void
emit_hs_driver_params(const struct ir3_shader_variant *v, fd_cs &dpconstobj,
struct fd_context *ctx)
{
if (CHIP == A7XX && ctx->screen->info->a7xx.load_shader_consts_via_preamble) {
if (CHIP == A7XX && ctx->screen->info->props.load_shader_consts_via_preamble) {
const struct ir3_const_state *const_state = ir3_const_state(v);
struct ir3_driver_params_tcs hs_params = ir3_build_driver_params_tcs(ctx);
int base = const_state->driver_params_ubo.idx;
@ -478,7 +478,7 @@ fd6_emit_cs_driver_params(struct fd_context *ctx, fd_cs &cs,
const struct ir3_shader_variant *v,
const struct pipe_grid_info *info)
{
if (CHIP == A7XX && ctx->screen->info->a7xx.load_shader_consts_via_preamble) {
if (CHIP == A7XX && ctx->screen->info->props.load_shader_consts_via_preamble) {
const struct ir3_const_state *const_state = ir3_const_state(v);
struct ir3_driver_params_cs compute_params =
ir3_build_driver_params_cs(v, info);

30
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -770,7 +770,7 @@ fd6_emit_ccu_cntl(fd_cs &cs, struct fd_screen *screen, bool gmem)
{
const struct fd6_gmem_config *cfg = gmem ? &screen->config_gmem : &screen->config_sysmem;
enum a6xx_ccu_cache_size color_cache_size = !gmem ? CCU_CACHE_SIZE_FULL :
(enum a6xx_ccu_cache_size)(screen->info->a6xx.gmem_ccu_color_cache_fraction);
(enum a6xx_ccu_cache_size)(screen->info->props.gmem_ccu_color_cache_fraction);
uint32_t color_offset = cfg->color_ccu_offset & 0x1fffff;
uint32_t color_offset_hi = cfg->color_ccu_offset >> 21;
@ -789,7 +789,7 @@ fd6_emit_ccu_cntl(fd_cs &cs, struct fd_screen *screen, bool gmem)
)
);
if (screen->info->a7xx.has_gmem_vpc_attr_buf) {
if (screen->info->props.has_gmem_vpc_attr_buf) {
fd_crb(cs, 3)
.add(VPC_ATTR_BUF_GMEM_SIZE(CHIP, cfg->vpc_attr_buf_size))
.add(VPC_ATTR_BUF_GMEM_BASE(CHIP, cfg->vpc_attr_buf_offset))
@ -801,9 +801,9 @@ fd6_emit_ccu_cntl(fd_cs &cs, struct fd_screen *screen, bool gmem)
fd_pkt4(cs, 1)
.add(RB_CCU_CNTL(CHIP,
.gmem_fast_clear_disable =
!screen->info->a6xx.has_gmem_fast_clear,
!screen->info->props.has_gmem_fast_clear,
.concurrent_resolve =
screen->info->a6xx.concurrent_resolve,
screen->info->props.concurrent_resolve,
.depth_offset_hi = depth_offset_hi,
.color_offset_hi = color_offset_hi,
.depth_cache_size = CCU_CACHE_SIZE_FULL,
@ -832,7 +832,7 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs)
{
struct fd_screen *screen = ctx->screen;
fd_ncrb<CHIP> ncrb(cs, 28 + ARRAY_SIZE(screen->info->a6xx.magic_raw));
fd_ncrb<CHIP> ncrb(cs, 28 + ARRAY_SIZE(screen->info->props.magic_raw));
if (CHIP >= A7XX) {
/* On A7XX, RB_CCU_CNTL was broken into two registers, RB_CCU_CNTL which has
@ -842,13 +842,13 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs)
* events are required.
*/
ncrb.add(RB_CCU_CNTL(CHIP,
.gmem_fast_clear_disable = true, // !screen->info->a6xx.has_gmem_fast_clear,
.concurrent_resolve = screen->info->a6xx.concurrent_resolve,
.gmem_fast_clear_disable = true, // !screen->info->props.has_gmem_fast_clear,
.concurrent_resolve = screen->info->props.concurrent_resolve,
));
}
for (size_t i = 0; i < ARRAY_SIZE(screen->info->a6xx.magic_raw); i++) {
auto magic_reg = screen->info->a6xx.magic_raw[i];
for (size_t i = 0; i < ARRAY_SIZE(screen->info->props.magic_raw); i++) {
auto magic_reg = screen->info->props.magic_raw[i];
if (!magic_reg.reg)
break;
@ -856,7 +856,7 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs)
switch(magic_reg.reg) {
case REG_A6XX_TPL1_DBG_ECO_CNTL1:
value = (value & ~A6XX_TPL1_DBG_ECO_CNTL1_TP_UBWC_FLAG_HINT) |
(screen->info->a7xx.enable_tp_ubwc_flag_hint
(screen->info->props.enable_tp_ubwc_flag_hint
? A6XX_TPL1_DBG_ECO_CNTL1_TP_UBWC_FLAG_HINT
: 0);
break;
@ -865,11 +865,11 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs)
ncrb.add({ .reg = magic_reg.reg, .value = value });
}
ncrb.add(A6XX_RB_DBG_ECO_CNTL(.dword = screen->info->a6xx.magic.RB_DBG_ECO_CNTL));
ncrb.add(A6XX_RB_DBG_ECO_CNTL(.dword = screen->info->props.magic.RB_DBG_ECO_CNTL));
ncrb.add(A6XX_SP_NC_MODE_CNTL_2(.f16_no_inf = true));
ncrb.add(A6XX_SP_PERFCTR_SHADER_MASK(.dword = 0x3f));
if (CHIP == A6XX && !screen->info->a6xx.is_a702)
if (CHIP == A6XX && !screen->info->props.is_a702)
ncrb.add(TPL1_UNKNOWN_B605(CHIP, .dword = 0x44));
if (CHIP == A6XX) {
ncrb.add(HLSQ_UNKNOWN_BE00(CHIP, .dword = 0x80));
@ -893,7 +893,7 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs)
ncrb.add(TPL1_BICUBIC_WEIGHTS_TABLE_REG(CHIP, 4, 0x3f0243f0));
}
if (screen->info->a7xx.has_hw_bin_scaling) {
if (screen->info->props.has_hw_bin_scaling) {
ncrb.add(GRAS_BIN_FOVEAT(CHIP));
ncrb.add(RB_BIN_FOVEAT(CHIP));
}
@ -920,7 +920,7 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs)
crb.add(SP_GFX_USIZE(CHIP));
crb.add(A6XX_TPL1_PS_ROTATION_CNTL());
crb.add(A6XX_RB_RBP_CNTL(.dword = screen->info->a6xx.magic.RB_RBP_CNTL));
crb.add(A6XX_RB_RBP_CNTL(.dword = screen->info->props.magic.RB_RBP_CNTL));
crb.add(A6XX_SP_UNKNOWN_A9A8());
crb.add(A6XX_SP_MODE_CNTL(
@ -1033,7 +1033,7 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs)
* so any leftover early preamble doesn't get executed. Other stages don't
* seem to be affected.
*/
if (screen->info->a6xx.has_early_preamble) {
if (screen->info->props.has_early_preamble) {
crb.add(A6XX_SP_PS_CNTL_0());
}
}

36
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -305,13 +305,13 @@ emit_lrz_clears(struct fd_batch *batch)
fd6_emit_flushes<CHIP>(ctx, cs, FD6_FLUSH_CACHE);
if (ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit !=
ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL) {
if (ctx->screen->info->props.magic.RB_DBG_ECO_CNTL_blit !=
ctx->screen->info->props.magic.RB_DBG_ECO_CNTL) {
/* This a non-context register, so we have to WFI before changing. */
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd_pkt4(cs, 1)
.add(A6XX_RB_DBG_ECO_CNTL(
.dword = ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit
.dword = ctx->screen->info->props.magic.RB_DBG_ECO_CNTL_blit
));
}
}
@ -325,12 +325,12 @@ emit_lrz_clears(struct fd_batch *batch)
if (count > 0) {
fd_cs cs(fd_batch_get_prologue(batch));
if (ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit !=
ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL) {
if (ctx->screen->info->props.magic.RB_DBG_ECO_CNTL_blit !=
ctx->screen->info->props.magic.RB_DBG_ECO_CNTL) {
fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0);
fd_pkt4(cs, 1)
.add(A6XX_RB_DBG_ECO_CNTL(
.dword = ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL
.dword = ctx->screen->info->props.magic.RB_DBG_ECO_CNTL
));
}
@ -457,7 +457,7 @@ patch_fb_read_sysmem(struct fd_batch *batch)
const struct fdl_layout *layouts[3] = {&rsc->layout, NULL, NULL};
struct fdl6_view view;
fdl6_view_init<CHIP>(&view, layouts, &args,
batch->ctx->screen->info->a6xx.has_z24uint_s8uint);
batch->ctx->screen->info->props.has_z24uint_s8uint);
memcpy(patch->cs, view.descriptor, FDL6_TEX_CONST_DWORDS * 4);
}
@ -513,7 +513,7 @@ update_render_cntl(fd_cs &cs, struct fd_screen *screen,
.flag_mrts = mrts_ubwc_enable,
);
if (screen->info->a6xx.has_cp_reg_write) {
if (screen->info->props.has_cp_reg_write) {
fd_pkt7(cs, CP_REG_WRITE, 3)
.add(CP_REG_WRITE_0(TRACK_RENDER_CNTL))
.add(CP_REG_WRITE_1(rb_render_cntl.reg))
@ -734,7 +734,7 @@ emit_common_init(fd_cs &cs, struct fd_batch *batch)
fd_pkt4(cs, 1)
.add(A6XX_RB_SAMPLE_COUNTER_CNTL(.copy = true));
if (!ctx->screen->info->a7xx.has_event_write_sample_count) {
if (!ctx->screen->info->props.has_event_write_sample_count) {
fd_pkt4(cs, 2)
.add(A6XX_RB_SAMPLE_COUNTER_BASE(
results_ptr(at, result[result->idx].samples_start)
@ -773,7 +773,7 @@ emit_common_fini(fd_cs &cs, struct fd_batch *batch)
cs.attach_bo(at->results_mem);
if (!ctx->screen->info->a7xx.has_event_write_sample_count) {
if (!ctx->screen->info->props.has_event_write_sample_count) {
with_crb (cs, 3) {
crb.add(A6XX_RB_SAMPLE_COUNTER_CNTL(.copy = true));
crb.add(A6XX_RB_SAMPLE_COUNTER_BASE(
@ -1160,9 +1160,9 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
set_bin_size<CHIP>(crb, gmem, {
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = !screen->info->a6xx.has_lrz_feedback,
.force_lrz_write_dis = !screen->info->props.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = screen->info->a6xx.has_lrz_feedback
.lrz_feedback_zmode_mask = screen->info->props.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE,
});
@ -1191,10 +1191,10 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
set_bin_size<CHIP>(crb, gmem, {
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = !screen->info->a6xx.has_lrz_feedback,
.force_lrz_write_dis = !screen->info->props.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask =
screen->info->a6xx.has_lrz_feedback
screen->info->props.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE,
});
@ -1293,9 +1293,9 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
set_bin_size<CHIP>(crb, gmem, {
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = !screen->info->a6xx.has_lrz_feedback,
.force_lrz_write_dis = !screen->info->props.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = screen->info->a6xx.has_lrz_feedback
.lrz_feedback_zmode_mask = screen->info->props.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE,
});
@ -1319,9 +1319,9 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
set_bin_size<CHIP>(crb, gmem, {
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = !screen->info->a6xx.has_lrz_feedback,
.force_lrz_write_dis = !screen->info->props.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = screen->info->a6xx.has_lrz_feedback
.lrz_feedback_zmode_mask = screen->info->props.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE,
});

4
src/gallium/drivers/freedreno/a6xx/fd6_image.cc
View file

@ -72,7 +72,7 @@ fd6_image_descriptor(struct fd_context *ctx, const struct pipe_image_view *buf,
struct fdl6_view view;
fdl6_view_init<CHIP>(&view, &layouts, &args,
ctx->screen->info->a6xx.has_z24uint_s8uint);
ctx->screen->info->props.has_z24uint_s8uint);
memcpy(descriptor, view.storage_descriptor, sizeof(view.storage_descriptor));
} else if (buf->resource->target == PIPE_BUFFER) {
@ -112,7 +112,7 @@ fd6_image_descriptor(struct fd_context *ctx, const struct pipe_image_view *buf,
struct fd_resource *rsc = fd_resource(buf->resource);
const struct fdl_layout *layouts[3] = { &rsc->layout, NULL, NULL };
fdl6_view_init<CHIP>(&view, layouts, &args,
ctx->screen->info->a6xx.has_z24uint_s8uint);
ctx->screen->info->props.has_z24uint_s8uint);
memcpy(descriptor, view.storage_descriptor, sizeof(view.storage_descriptor));
}

16
src/gallium/drivers/freedreno/a6xx/fd6_program.cc
View file

@ -186,7 +186,7 @@ emit_shader_regs(struct fd_context *ctx, fd_cs &cs, const struct ir3_shader_vari
crb.add(SP_PS_VGS_CNTL(CHIP));
break;
case MESA_SHADER_COMPUTE:
thrsz = ctx->screen->info->a6xx.supports_double_threadsize ? thrsz : THREAD128;
thrsz = ctx->screen->info->props.supports_double_threadsize ? thrsz : THREAD128;
crb.add(A6XX_SP_CS_CNTL_0(
.halfregfootprint = so->info.max_half_reg + 1,
.fullregfootprint = so->info.max_reg + 1,
@ -235,7 +235,7 @@ fd6_emit_shader(struct fd_context *ctx, fd_cs &cs, const struct ir3_shader_varia
if (CHIP == A6XX) {
uint32_t shader_preload_size =
MIN2(so->instrlen, ctx->screen->info->a6xx.instr_cache_size);
MIN2(so->instrlen, ctx->screen->info->props.instr_cache_size);
fd_pkt7(cs, fd6_stage2opcode(so->type), 3)
.add(CP_LOAD_STATE6_0(
@ -261,7 +261,7 @@ setup_stream_out_disable(struct fd_context *ctx)
{
unsigned nreg = 2;
if (ctx->screen->info->a6xx.tess_use_shared)
if (ctx->screen->info->props.tess_use_shared)
nreg++;
fd_crb crb(ctx->pipe, nreg);
@ -269,7 +269,7 @@ setup_stream_out_disable(struct fd_context *ctx)
crb.add(VPC_SO_MAPPING_WPTR(CHIP));
crb.add(VPC_SO_CNTL(CHIP));
if (ctx->screen->info->a6xx.tess_use_shared) {
if (ctx->screen->info->props.tess_use_shared) {
crb.add(PC_DGEN_SO_CNTL(CHIP));
}
@ -334,7 +334,7 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
}
const bool emit_pc_so_stream_cntl =
ctx->screen->info->a6xx.tess_use_shared &&
ctx->screen->info->props.tess_use_shared &&
v->type == MESA_SHADER_TESS_EVAL;
unsigned nreg = 5 + prog_count;
@ -664,7 +664,7 @@ emit_vpc(fd_crb &crb, const struct program_builder *b)
* an input primitive type with adjacency, an output primitive type of
* points, and a high enough vertex count causes a hang.
*/
if (b->ctx->screen->info->a7xx.gs_vpc_adjacency_quirk &&
if (b->ctx->screen->info->props.gs_vpc_adjacency_quirk &&
b->gs && b->gs->gs.output_primitive == MESA_PRIM_POINTS &&
linkage.max_loc > 4) {
linkage.max_loc = MAX2(linkage.max_loc, 9);
@ -1055,7 +1055,7 @@ emit_fs_inputs(fd_crb &crb, const struct program_builder *b)
}
}
crb.add(SP_LB_PARAM_LIMIT(CHIP, b->ctx->screen->info->a6xx.prim_alloc_threshold));
crb.add(SP_LB_PARAM_LIMIT(CHIP, b->ctx->screen->info->props.prim_alloc_threshold));
crb.add(SP_REG_PROG_ID_0(CHIP,
.faceregid = face_regid,
.sampleid = samp_id_regid,
@ -1264,7 +1264,7 @@ setup_stateobj(fd_cs &cs, const struct program_builder *b)
const uint32_t vs_hs_local_mem_size = 16384;
uint32_t max_patches_per_wave;
if (b->ctx->screen->info->a6xx.tess_use_shared) {
if (b->ctx->screen->info->props.tess_use_shared) {
/* HS invocations for a patch are always within the same wave,
* making barriers less expensive. VS can't have barriers so we
* don't care about VS invocations being in the same wave.

6
src/gallium/drivers/freedreno/a6xx/fd6_query.cc
View file

@ -66,7 +66,7 @@ occlusion_resume(struct fd_acc_query *aq, struct fd_batch *batch)
fd_pkt4(cs, 1)
.add(A6XX_RB_SAMPLE_COUNTER_CNTL(.copy = true));
if (!ctx->screen->info->a7xx.has_event_write_sample_count) {
if (!ctx->screen->info->props.has_event_write_sample_count) {
fd_pkt4(cs, 2)
.add(A6XX_RB_SAMPLE_COUNTER_BASE(query_sample(aq, start)));
@ -109,7 +109,7 @@ occlusion_pause(struct fd_acc_query *aq, struct fd_batch *batch) assert_dt
struct fd_context *ctx = batch->ctx;
fd_cs cs(batch->draw);
if (!ctx->screen->info->a7xx.has_event_write_sample_count) {
if (!ctx->screen->info->props.has_event_write_sample_count) {
fd_pkt7(cs, CP_MEM_WRITE, 4)
.add(A5XX_CP_MEM_WRITE_ADDR(query_sample(aq, stop)))
.add(0xffffffff)
@ -123,7 +123,7 @@ occlusion_pause(struct fd_acc_query *aq, struct fd_batch *batch) assert_dt
ASSERT_ALIGNED(struct fd6_query_sample, stop, 16);
if (!ctx->screen->info->a7xx.has_event_write_sample_count) {
if (!ctx->screen->info->props.has_event_write_sample_count) {
fd_pkt4(cs, 2)
.add(A6XX_RB_SAMPLE_COUNTER_BASE(query_sample(aq, stop)));

4
src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.cc
View file

@ -95,7 +95,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
crb.add(PC_DGEN_RAST_CNTL(CHIP, mode));
if (CHIP == A7XX ||
(CHIP == A6XX && ctx->screen->info->a6xx.is_a702)) {
(CHIP == A6XX && ctx->screen->info->props.is_a702)) {
crb.add(VPC_PS_RAST_CNTL(CHIP, mode));
}
@ -119,7 +119,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
crb.add(RB_VIEWPORT_ZCLAMP_MAX(CHIP, 1.0f));
}
if (CHIP == A6XX && ctx->screen->info->a6xx.has_legacy_pipeline_shading_rate) {
if (CHIP == A6XX && ctx->screen->info->props.has_legacy_pipeline_shading_rate) {
crb.add(RB_UNKNOWN_8A00(CHIP));
crb.add(RB_UNKNOWN_8A10(CHIP));
crb.add(RB_UNKNOWN_8A20(CHIP));

14
src/gallium/drivers/freedreno/a6xx/fd6_resource.cc
View file

@ -31,13 +31,13 @@ ok_ubwc_format(struct pipe_screen *pscreen, enum pipe_format pfmt, unsigned nr_s
/*
* TODO: no UBWC on a702?
*/
if (info->a6xx.is_a702)
if (info->props.is_a702)
return false;
switch (pfmt) {
case PIPE_FORMAT_Z24X8_UNORM:
/* MSAA+UBWC does not work without FMT6_Z24_UINT_S8_UINT: */
return info->a6xx.has_z24uint_s8uint || (nr_samples <= 1);
return info->props.has_z24uint_s8uint || (nr_samples <= 1);
case PIPE_FORMAT_X24S8_UINT:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
@ -46,7 +46,7 @@ ok_ubwc_format(struct pipe_screen *pscreen, enum pipe_format pfmt, unsigned nr_s
* fd_resource_uncompress() at the point of stencil sampling because
* that itself uses stencil sampling in the fd_blitter_blit path.
*/
return info->a6xx.has_z24uint_s8uint;
return info->props.has_z24uint_s8uint;
case PIPE_FORMAT_R8_G8B8_420_UNORM:
/* The difference between NV12 and R8_G8B8_420_UNORM is only where the
@ -67,7 +67,7 @@ ok_ubwc_format(struct pipe_screen *pscreen, enum pipe_format pfmt, unsigned nr_s
* all 1's prior to a740. Disable UBWC for snorm.
*/
if (util_format_is_snorm(pfmt) &&
!info->a7xx.ubwc_unorm_snorm_int_compatible)
!info->props.ubwc_unorm_snorm_int_compatible)
return false;
/* A690 seem to have broken UBWC for depth/stencil, it requires
@ -75,7 +75,7 @@ ok_ubwc_format(struct pipe_screen *pscreen, enum pipe_format pfmt, unsigned nr_s
* ordinary draw calls writing read/depth. WSL blob seem to use ubwc
* sometimes for depth/stencil.
*/
if (info->a6xx.broken_ds_ubwc_quirk &&
if (info->props.broken_ds_ubwc_quirk &&
util_format_is_depth_or_stencil(pfmt))
return false;
@ -109,7 +109,7 @@ ok_ubwc_format(struct pipe_screen *pscreen, enum pipe_format pfmt, unsigned nr_s
case FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8:
return true;
case FMT6_8_UNORM:
return info->a6xx.has_8bpp_ubwc;
return info->props.has_8bpp_ubwc;
default:
return false;
}
@ -150,7 +150,7 @@ valid_ubwc_format_cast(struct fd_resource *rsc, enum pipe_format format)
/* If we support z24s8 ubwc then allow casts between the various
* permutations of z24s8:
*/
if (info->a6xx.has_z24uint_s8uint && is_z24s8(format) && is_z24s8(orig_format))
if (info->props.has_z24uint_s8uint && is_z24s8(format) && is_z24s8(orig_format))
return true;
enum fd6_ubwc_compat_type type = fd6_ubwc_compat_mode(info, orig_format);

12
src/gallium/drivers/freedreno/a6xx/fd6_screen.cc
View file

@ -170,12 +170,12 @@ fd6_screen_init(struct pipe_screen *pscreen)
screen->max_rts = A6XX_MAX_RENDER_TARGETS;
uint32_t depth_cache_size =
screen->info->num_ccu * screen->info->a6xx.sysmem_per_ccu_depth_cache_size;
screen->info->num_ccu * screen->info->props.sysmem_per_ccu_depth_cache_size;
uint32_t color_cache_size =
(screen->info->num_ccu * screen->info->a6xx.sysmem_per_ccu_color_cache_size);
(screen->info->num_ccu * screen->info->props.sysmem_per_ccu_color_cache_size);
uint32_t color_cache_size_gmem =
color_cache_size /
(1 << screen->info->a6xx.gmem_ccu_color_cache_fraction);
(1 << screen->info->props.gmem_ccu_color_cache_fraction);
struct fd6_gmem_config *gmem = &screen->config_gmem;
struct fd6_gmem_config *sysmem = &screen->config_sysmem;
@ -183,11 +183,11 @@ fd6_screen_init(struct pipe_screen *pscreen)
sysmem->depth_ccu_offset = 0;
sysmem->color_ccu_offset = sysmem->depth_ccu_offset + depth_cache_size;
if (screen->info->a7xx.has_gmem_vpc_attr_buf) {
sysmem->vpc_attr_buf_size = screen->info->a7xx.sysmem_vpc_attr_buf_size;
if (screen->info->props.has_gmem_vpc_attr_buf) {
sysmem->vpc_attr_buf_size = screen->info->props.sysmem_vpc_attr_buf_size;
sysmem->vpc_attr_buf_offset = sysmem->color_ccu_offset + color_cache_size;
gmem->vpc_attr_buf_size = screen->info->a7xx.gmem_vpc_attr_buf_size;
gmem->vpc_attr_buf_size = screen->info->props.gmem_vpc_attr_buf_size;
gmem->vpc_attr_buf_offset = screen->gmemsize_bytes -
(gmem->vpc_attr_buf_size * screen->info->num_ccu);

6
src/gallium/drivers/freedreno/a6xx/fd6_texture.cc
View file

@ -96,7 +96,7 @@ setup_border_color(struct fd_screen *screen,
struct fd6_bcolor_entry *e)
{
STATIC_ASSERT(sizeof(struct fd6_bcolor_entry) == FD6_BORDER_COLOR_SIZE);
const bool has_z24uint_s8uint = screen->info->a6xx.has_z24uint_s8uint;
const bool has_z24uint_s8uint = screen->info->props.has_z24uint_s8uint;
const union pipe_color_union *bc = &sampler->border_color;
enum pipe_format format = sampler->border_color_format;
@ -462,7 +462,7 @@ fd6_sampler_view_update(struct fd_context *ctx,
struct fdl6_view view;
fdl6_view_init<CHIP>(&view, &layouts, &args,
ctx->screen->info->a6xx.has_z24uint_s8uint);
ctx->screen->info->props.has_z24uint_s8uint);
memcpy(so->descriptor, view.descriptor, sizeof(so->descriptor));
} else if (cso->target == PIPE_BUFFER) {
@ -511,7 +511,7 @@ fd6_sampler_view_update(struct fd_context *ctx,
};
struct fdl6_view view;
fdl6_view_init<CHIP>(&view, layouts, &args,
ctx->screen->info->a6xx.has_z24uint_s8uint);
ctx->screen->info->props.has_z24uint_s8uint);
memcpy(so->descriptor, view.descriptor, sizeof(so->descriptor));
}
}

2
src/gallium/drivers/freedreno/a6xx/fd6_zsa.cc
View file

@ -100,7 +100,7 @@ fd6_zsa_state_create(struct pipe_context *pctx,
* dEQP-VK.dynamic_state.ds_state.depth_bounds_1
*/
if (cso->depth_bounds_test && !cso->depth_enabled &&
ctx->screen->info->a6xx.depth_bounds_require_depth_test_quirk) {
ctx->screen->info->props.depth_bounds_require_depth_test_quirk) {
force_z_test_enable = true;
depth_func = FUNC_ALWAYS;
}

2
src/gallium/drivers/freedreno/freedreno_resource.c
View file

@ -1295,7 +1295,7 @@ get_best_layout(struct fd_screen *screen,
return FD_LAYOUT_LINEAR;
}
bool ubwc_ok = is_a6xx(screen) && !screen->info->a6xx.is_a702;
bool ubwc_ok = is_a6xx(screen) && !screen->info->props.is_a702;
if (FD_DBG(NOUBWC))
ubwc_ok = false;

18
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -214,7 +214,7 @@ fd_init_shader_caps(struct fd_screen *screen)
case MESA_SHADER_GEOMETRY:
if (!is_a6xx(screen))
continue;
if (screen->info->a6xx.is_a702)
if (screen->info->props.is_a702)
continue;
break;
case MESA_SHADER_COMPUTE:
@ -233,10 +233,10 @@ fd_init_shader_caps(struct fd_screen *screen)
caps->max_control_flow_depth = 8; /* XXX */
caps->max_inputs = is_a6xx(screen) && i != MESA_SHADER_GEOMETRY ?
screen->info->a6xx.vs_max_inputs_count : 16;
screen->info->props.vs_max_inputs_count : 16;
caps->max_outputs =
(is_a6xx(screen) && !screen->info->a6xx.is_a702) ? 32 : 16;
(is_a6xx(screen) && !screen->info->props.is_a702) ? 32 : 16;
caps->max_temps = 64; /* Max native temporaries. */
@ -337,7 +337,7 @@ fd_init_compute_caps(struct fd_screen *screen)
caps->max_threads_per_block = info->threadsize_base * info->max_waves;
if (is_a6xx(screen) && info->a6xx.supports_double_threadsize)
if (is_a6xx(screen) && info->props.supports_double_threadsize)
caps->max_threads_per_block *= 2;
caps->max_global_size = screen->ram_size;
@ -446,10 +446,10 @@ fd_init_screen_caps(struct fd_screen *screen)
caps->sampler_reduction_minmax =
caps->sampler_reduction_minmax_arb =
is_a6xx(screen) && screen->info->a6xx.has_sampler_minmax;
is_a6xx(screen) && screen->info->props.has_sampler_minmax;
caps->programmable_sample_locations =
is_a6xx(screen) && screen->info->a6xx.has_sample_locations;
is_a6xx(screen) && screen->info->props.has_sample_locations;
caps->polygon_offset_clamp = is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
@ -489,7 +489,7 @@ fd_init_screen_caps(struct fd_screen *screen)
caps->doubles = is_ir3(screen);
if (is_a6xx(screen)) {
if (screen->info->a6xx.is_a702) {
if (screen->info->props.is_a702) {
/* a702 family is a special case, no gs/tess: */
caps->glsl_feature_level = 140;
caps->essl_feature_level = 310;
@ -548,7 +548,7 @@ fd_init_screen_caps(struct fd_screen *screen)
caps->max_viewports = is_a6xx(screen) ? 16 : 1;
caps->max_varyings = (is_a6xx(screen) && !screen->info->a6xx.is_a702) ? 31 : 16;
caps->max_varyings = (is_a6xx(screen) && !screen->info->props.is_a702) ? 31 : 16;
/* We don't really have a limit on this, it all goes into the main
* memory buffer. Needs to be at least 120 / 4 (minimum requirement
@ -596,7 +596,7 @@ fd_init_screen_caps(struct fd_screen *screen)
/* Stream output. */
caps->max_vertex_streams =
(is_a6xx(screen) && !screen->info->a6xx.is_a702) ? /* has SO + GS */
(is_a6xx(screen) && !screen->info->props.is_a702) ? /* has SO + GS */
PIPE_MAX_SO_BUFFERS : 0;
caps->max_stream_output_buffers = is_ir3(screen) ? PIPE_MAX_SO_BUFFERS : 0;
caps->stream_output_pause_resume =

2
src/gallium/drivers/freedreno/ir3/ir3_gallium.c
View file

@ -293,7 +293,7 @@ ir3_shader_compute_state_create(struct pipe_context *pctx,
if (ctx->screen->gen >= 6)
ir3_nir_lower_io_to_bindless(nir);
if (ctx->screen->gen >= 6 && !ctx->screen->info->a6xx.supports_double_threadsize) {
if (ctx->screen->gen >= 6 && !ctx->screen->info->props.supports_double_threadsize) {
api_wavesize = IR3_SINGLE_ONLY;
real_wavesize = IR3_SINGLE_ONLY;
}