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freedreno: Move *_POWER_CNTL to raw_magic_regs

Browse source 
These two regs only exist in a6xx.  And only need a static value.  So
move them to raw_magic_regs and drop the fd_dev_info field and
corresponding driver code.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
This commit is contained in:
Rob Clark 2025-11-18 10:50:07 -08:00 • committed by Marge Bot
parent 31d69602d8
commit e81defa52d
5 changed files with 63 additions and 81 deletions
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1
src/freedreno/common/freedreno_dev_info.h
View file

@ -227,7 +227,6 @@ struct fd_dev_info {
bool is_a702;
struct {
uint32_t PC_POWER_CNTL;
uint32_t TPL1_DBG_ECO_CNTL;
uint32_t GRAS_DBG_ECO_CNTL;
uint32_t SP_CHICKEN_BITS;

85
src/freedreno/common/freedreno_devices.py
View file

@ -468,7 +468,6 @@ add_gpus([
ubwc_swizzle = 0x7,
macrotile_mode = 0,
magic_regs = dict(
PC_POWER_CNTL = 0,
TPL1_DBG_ECO_CNTL = 0,
GRAS_DBG_ECO_CNTL = 0,
SP_CHICKEN_BITS = 0,
@ -482,6 +481,10 @@ add_gpus([
VPC_DBG_ECO_CNTL = 0x0,
UCHE_UNKNOWN_0E12 = 0x10000000,
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 0],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 0],
],
))
add_gpus([
@ -502,7 +505,6 @@ add_gpus([
highest_bank_bit = 14,
macrotile_mode = 0,
magic_regs = dict(
PC_POWER_CNTL = 0,
TPL1_DBG_ECO_CNTL = 0x00108000,
GRAS_DBG_ECO_CNTL = 0x00000880,
SP_CHICKEN_BITS = 0x00000430,
@ -515,7 +517,11 @@ add_gpus([
RB_RBP_CNTL = 0x00000001,
VPC_DBG_ECO_CNTL = 0x0,
UCHE_UNKNOWN_0E12 = 0x00000001
)
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 0],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 0],
],
))
add_gpus([
@ -531,7 +537,6 @@ add_gpus([
wave_granularity = 2,
fibers_per_sp = 128 * 16,
magic_regs = dict(
PC_POWER_CNTL = 0,
TPL1_DBG_ECO_CNTL = 0x01008000,
GRAS_DBG_ECO_CNTL = 0x0,
SP_CHICKEN_BITS = 0x00000400,
@ -544,7 +549,11 @@ add_gpus([
RB_RBP_CNTL = 0x0,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000001
)
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 0],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 0],
],
))
add_gpus([
@ -561,7 +570,6 @@ add_gpus([
wave_granularity = 2,
fibers_per_sp = 128 * 2 * 16,
magic_regs = dict(
PC_POWER_CNTL = 0,
# this seems to be a chicken bit that fixes cubic filtering:
TPL1_DBG_ECO_CNTL = 0x01008000,
GRAS_DBG_ECO_CNTL = 0x0,
@ -575,7 +583,11 @@ add_gpus([
RB_RBP_CNTL = 0x0,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000001
)
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 0],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 0],
],
))
add_gpus([
@ -593,7 +605,6 @@ add_gpus([
highest_bank_bit = 15,
macrotile_mode = 0,
magic_regs = dict(
PC_POWER_CNTL = 1,
TPL1_DBG_ECO_CNTL = 0x00108000,
GRAS_DBG_ECO_CNTL = 0x00000880,
SP_CHICKEN_BITS = 0x00001430,
@ -606,7 +617,11 @@ add_gpus([
RB_RBP_CNTL = 0x00000001,
VPC_DBG_ECO_CNTL = 0x0,
UCHE_UNKNOWN_0E12 = 0x10000001
)
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 1],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 1],
],
))
add_gpus([
@ -624,7 +639,6 @@ add_gpus([
highest_bank_bit = 15,
macrotile_mode = 0,
magic_regs = dict(
PC_POWER_CNTL = 1,
TPL1_DBG_ECO_CNTL = 0x00008000,
GRAS_DBG_ECO_CNTL = 0x0,
SP_CHICKEN_BITS = 0x00000420,
@ -637,7 +651,11 @@ add_gpus([
RB_RBP_CNTL = 0x00000001,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000001
)
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 1],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 1],
],
))
add_gpus([
@ -655,7 +673,6 @@ add_gpus([
highest_bank_bit = 15,
macrotile_mode = 0,
magic_regs = dict(
PC_POWER_CNTL = 3,
TPL1_DBG_ECO_CNTL = 0x00108000,
GRAS_DBG_ECO_CNTL = 0x0,
SP_CHICKEN_BITS = 0x00001430,
@ -668,7 +685,11 @@ add_gpus([
RB_RBP_CNTL = 0x00000001,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000001
)
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 3],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 3],
],
))
add_gpus([
@ -685,7 +706,6 @@ add_gpus([
fibers_per_sp = 128 * 2 * 16,
highest_bank_bit = 16,
magic_regs = dict(
PC_POWER_CNTL = 2,
# this seems to be a chicken bit that fixes cubic filtering:
TPL1_DBG_ECO_CNTL = 0x01008000,
GRAS_DBG_ECO_CNTL = 0x0,
@ -699,7 +719,11 @@ add_gpus([
RB_RBP_CNTL = 0x0,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000001
)
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 2],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 2],
],
))
add_gpus([
@ -722,7 +746,6 @@ add_gpus([
fibers_per_sp = 128 * 2 * 16,
highest_bank_bit = 14,
magic_regs = dict(
PC_POWER_CNTL = 1,
TPL1_DBG_ECO_CNTL = 0x05008000,
GRAS_DBG_ECO_CNTL = 0x0,
SP_CHICKEN_BITS = 0x00001400,
@ -735,7 +758,11 @@ add_gpus([
RB_RBP_CNTL = 0x0,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000001
)
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 1],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 1],
],
))
add_gpus([
@ -752,7 +779,6 @@ add_gpus([
fibers_per_sp = 128 * 2 * 16,
highest_bank_bit = 16,
magic_regs = dict(
PC_POWER_CNTL = 2,
TPL1_DBG_ECO_CNTL = 0x05008000,
GRAS_DBG_ECO_CNTL = 0x0,
SP_CHICKEN_BITS = 0x00001400,
@ -765,7 +791,11 @@ add_gpus([
RB_RBP_CNTL = 0x0,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000001
)
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 2],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 2],
],
))
add_gpus([
@ -782,7 +812,6 @@ add_gpus([
wave_granularity = 2,
fibers_per_sp = 128 * 4 * 16,
magic_regs = dict(
PC_POWER_CNTL = 2,
TPL1_DBG_ECO_CNTL = 0x05008000,
GRAS_DBG_ECO_CNTL = 0x0,
SP_CHICKEN_BITS = 0x00001400,
@ -795,7 +824,11 @@ add_gpus([
RB_RBP_CNTL = 0x0,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000001
)
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 2],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 2],
],
))
add_gpus([
@ -813,7 +846,6 @@ add_gpus([
fibers_per_sp = 128 * 2 * 16,
highest_bank_bit = 16,
magic_regs = dict(
PC_POWER_CNTL = 7,
TPL1_DBG_ECO_CNTL = 0x04c00000,
GRAS_DBG_ECO_CNTL = 0x0,
SP_CHICKEN_BITS = 0x00001400,
@ -829,6 +861,8 @@ add_gpus([
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_SP_UNKNOWN_AAF2, 0x00c00000],
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 7],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 7],
],
))
@ -861,7 +895,6 @@ add_gpus([
max_waves = 16,
# has_early_preamble = True, # for VS/FS but not CS?
magic_regs = dict(
PC_POWER_CNTL = 0,
TPL1_DBG_ECO_CNTL = 0x8000,
GRAS_DBG_ECO_CNTL = 0,
SP_CHICKEN_BITS = 0x1400,
@ -875,6 +908,10 @@ add_gpus([
VPC_DBG_ECO_CNTL = 0x0,
UCHE_UNKNOWN_0E12 = 0x1,
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_PC_POWER_CNTL, 0],
[A6XXRegs.REG_A6XX_VFD_POWER_CNTL, 0],
],
))
# Based on a6xx_base + a6xx_gen4
@ -1035,7 +1072,6 @@ a730_raw_magic_regs = [
]
a740_magic_regs = dict(
# PC_POWER_CNTL = 7,
TPL1_DBG_ECO_CNTL = 0x11100000,
GRAS_DBG_ECO_CNTL = 0x00004800,
SP_CHICKEN_BITS = 0x10001400,
@ -1277,7 +1313,6 @@ add_gpus([
wave_granularity = 2,
fibers_per_sp = 128 * 2 * 16,
magic_regs = dict(
# PC_POWER_CNTL = 7,
TPL1_DBG_ECO_CNTL = 0x11100000,
GRAS_DBG_ECO_CNTL = 0x00004800,
SP_CHICKEN_BITS = 0x10001400,

4
src/freedreno/registers/adreno/a6xx.xml
View file

@ -3177,7 +3177,7 @@ by a particular renderpass/blit.
<reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" variants="A6XX-A7XX" usage="rp_blit"/>
<reg32 offset="0x9b00" name="PC_MODE_CNTL" low="0" high="14" variants="A8XX" usage="rp_blit"/>
<reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
<reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" variants="A6XX" usage="rp_blit"/>
<bitset name="a6xx_pc_ps_cntl" inline="yes">
<bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/>
@ -3457,7 +3457,7 @@ by a particular renderpass/blit.
</reg32>
</array>
<reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
<reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" variants="A6XX" usage="rp_blit"/>
<reg32 offset="0xa600" name="VFD_DBG_ECO_CNTL" variants="A7XX-" usage="init"/>

26
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -2140,22 +2140,12 @@ template <chip CHIP>
static void
tu_emit_bin_preamble(struct tu_device *dev, struct tu_cs *cs, bool bv)
{
struct tu_physical_device *phys_dev = dev->physical_device;
tu6_init_static_regs<CHIP>(dev, cs);
if (!bv)
emit_rb_ccu_cntl<CHIP>(cs, dev, true);
emit_vpc_attr_buf<CHIP>(cs, dev, true);
if (CHIP == A6XX) {
tu_cs_emit_regs(cs,
A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
tu_cs_emit_regs(cs,
A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
}
if (CHIP == A7XX && !bv) {
tu7_emit_tile_render_begin_regs(cs);
}
@ -2480,14 +2470,6 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
update_vsc_pipe(cmd, cs, phys_dev->info->num_vsc_pipes);
if (CHIP == A6XX) {
tu_cs_emit_regs(cs,
A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
tu_cs_emit_regs(cs,
A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
}
tu_emit_event_write<CHIP>(cmd, cs, FD_VSC_BINNING_START);
tu_cs_emit_regs(cs,
@ -3316,14 +3298,6 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
tu6_emit_binning_pass<CHIP>(cmd, cs, fdm_offsets, use_cb);
if (CHIP == A6XX) {
tu_cs_emit_regs(cs,
A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
tu_cs_emit_regs(cs,
A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
}
/* Enable early return from CP_INDIRECT_BUFFER once the visibility stream
* is done. We don't enable this if there are stores in a non-final
* subpass, because it's more important to be able to share gmem space

28
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -961,13 +961,6 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt
update_vsc_pipe<CHIP>(cs, batch);
if (CHIP == A6XX) {
fd_pkt4(cs, 1)
.add(A6XX_PC_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL));
fd_pkt4(cs, 1)
.add(A6XX_VFD_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL));
}
fd6_event_write<CHIP>(batch->ctx, cs, FD_VSC_BINNING_START);
fd_crb(cs, 2)
@ -1071,12 +1064,7 @@ fd6_build_preemption_preamble(struct fd_context *ctx)
fd6_emit_static_regs<CHIP>(cs, ctx);
fd6_emit_ccu_cntl<CHIP>(cs, screen, false);
if (CHIP == A6XX) {
fd_pkt4(cs, 1)
.add(A6XX_PC_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL));
fd_pkt4(cs, 1)
.add(A6XX_VFD_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL));
} else if (CHIP >= A7XX) {
if (CHIP >= A7XX) {
fd7_emit_static_binning_regs<CHIP>(cs);
}
@ -1182,13 +1170,6 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
crb.add(A6XX_VFD_RENDER_MODE(RENDERING_PASS));
}
if (CHIP == A6XX) {
fd_pkt4(cs, 1)
.add(A6XX_PC_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL));
fd_pkt4(cs, 1)
.add(A6XX_VFD_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL));
}
fd_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1)
.add(0x1);
@ -1322,13 +1303,6 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
crb.add(A6XX_VFD_RENDER_MODE(RENDERING_PASS));
}
if (CHIP == A6XX) {
fd_pkt4(cs, 1)
.add(A6XX_PC_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL));
fd_pkt4(cs, 1)
.add(A6XX_VFD_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL));
}
fd_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1)
.add(0x1);
} else {