Commit graph

33 commits

Author SHA1 Message Date
Marek Olšák
5425d32fcf amd/addrlib: update to the latest version for Vega12
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-28 11:37:43 -04:00
Marek Olšák
7f33e94e43 amd/addrlib: update to latest version
This uses C++11 initializer lists.

I just overwrote all Mesa files with internal addrlib and discarded
hunks that we should probably keep, but I might have missed something.

The code depending on ADDR_AM_BUILD is removed. We can add it back next
time if needed.

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-08 00:55:13 +01:00
Marek Olšák
c3f3685fd6 amd/addrlib: add Addr2IsValidDisplaySwizzleMode
Some "standard" (_S) swizzle modes are displayable on Raven,
even though the micro tile mode says it's not displayable.
Expose the addrlib function to the driver.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-12 19:03:33 +02:00
Dave Airlie
acf1e132af amd/addrlib: fix typo in api name.
This fixes the misspelling of ALIGNMENTS in addrlib.

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-07-17 01:44:14 +01:00
Marek Olšák
18e760346a amd/addrlib: second update for Vega10 + bug fixes
Highlights:
- Display needs tiled pitch alignment to be at least 32 pixels
- Implement Addr2ComputeDccAddrFromCoord().
- Macro-pixel packed formats don't support Z swizzle modes
- Pad pitch and base alignment of PRT + TEX1D to 64KB.
- Fix support for multimedia formats
- Fix a case "PRT" entries are not selected on SI.
- Fix wrong upper bits in equations for 3D resource.
- We can't support 2d array slice rotation in gfx8 swizzle pattern
- Set base alignment for PRT + non-xor swizzle mode resource to 64KB.
- Bug workaround for Z16 4x/8x and Z32 2x/4x/8x MSAA depth texture
- Add stereo support
- Optimize swizzle mode selection
- Report pitch and height in pixels for each mip
- Adjust bpp/expandX for format ADDR_FMT_GB_GR/ADDR_FMT_BG_RG
- Correct tcCompatible flag output for mipmap surface
- Other fixes and cleanups

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-04 11:14:43 +02:00
Nicolai Hähnle
7f160efcde amd/addrlib: import gfx9 support 2017-03-30 14:44:33 +02:00
Joe Ma
a489cdb20f amd/addrlib: Bump version to 6.02 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
11f1306207 amdgpu/addrlib: Bump version to 6.01
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
a136926eef amdgpu/addrlib: Seperate 2 dcc related workarounds by different flags
1) dccCompatible for padding MSAA surface to support fast clear
2) dccPipeWorkaround for padding surface to support dcc
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
48bf5d0800 amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calculated correctly 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
33c25655c1 amdgpu/addrlib: Add a new output flag to notify client that the returned tile index is for PRT on SI
If this flag is set for mip0, client should set prt flag for sub mips,
so that address lib can select the correct tile index for sub mips.
2017-03-30 14:44:33 +02:00
Xavi Zhang
fa906a888b amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixes
The usage should be client first call AddrComputeSurfaceInfo() on
depth surface with flag "matchStencilTilecfg", AddrLib will use
2DThin1 tile index for depth as much as possible and do not down grade
unless alignment requirement cannot be met.

1. If there is a matched 2DThin1 tile index for stencil which make
sure they will share same tile config parameters, then return the
stencil 2DThin1 tile index as well.
2. If using 2DThin1 tile mode cannot make sure such thing happen, and
TcCompatible flag was set, then ignore this flag then try 2DThin1 tile
mode for depth and stencil again.
3. If 2DThin1 tile mode cannot make sure depth and stencil to have
same tile config parameters, then down grade depth surface tile mode
to 1DThin1.
4. If depth surface's tile mode was 1DThin1, then return 1DThin1 tile
index for stencil.
5. If depth surface's tile mode is PRT, then return invalid tile index
to stencil since their tile config parameters will never be met.

Client driver then check the returned tile index of stencil -- if it
is not invalid tile index, then call AddrComputeSurfaceInfo() on
stencil surface with the returned stencil tile index to get full
output information. Please note, client needs to set flag
"useTileIndex" when AddrLib get created.
2017-03-30 14:44:33 +02:00
Frans Gu
6764d96eaa amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect ratio settings
By this way, we can have valid equation for 2D_THIN1 tile mode.
Add flag "preferEquation" to return equation index without adjusting
input tile mode.
2017-03-30 14:44:33 +02:00
Frans Gu
fe216415c6 amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlign
1) minimizePadding - Use 1D tile mode if padded size of 2D is bigger
than 1D
2) maxBaseAlign - Force PRT tile mode if macro block size is bigger than
requested alignment.

Also, related changes to tile mode optimization for needEquation.
2017-03-30 14:44:33 +02:00
Frans Gu
680f91e5d4 amdgpu/addrlib: Add flag to report if a surface can have dcc ram 2017-03-30 14:44:33 +02:00
Xavi Zhang
145750efba amdgpu/addrlib: Fix number of //
Find ^/{80,99}$  and replace them to 100 "/"

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Kevin Zhao
8912862a40 amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignment
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Frans Gu
acaeae2861 amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWN
This can be used by address lib client to ask address lib to select
tile mode.
2017-03-30 14:44:33 +02:00
Xavi Zhang
199912a9bc amdgpu/addrlib: Add a flag to skip calculate indices
This is useful for debugging and special cases for stencil surfaces
do not require texture fetch compatible.
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
10f7d1cb03 amdgpu/addrlib: add equation generation
1. Add new surface flags needEquation for client driver use to force
the surface tile setting equation compatible. Override 2D/3D macro
tile mode to PRT_* tile mode if this flag is TRUE and num slice > 1.
2. Add numEquations and pEquationTable in ADDR_CREATE_OUTPUT structure
to return number of equations and the equation table to client driver
3. Add equationIndex in ADDR_COMPUTE_SURFACE_INFO_OUTPUT structure to
return the equation index to client driver

Please note the use of address equation has following restrictions:
1) The surface can't be splitable
2) The surface can't have non zero tile swizzle value
3) Surface with > 1 slices must have PRT tile mode, which disable
slice rotation
2017-03-30 14:44:33 +02:00
Frans Gu
7293a020bd amdgpu/addrlib: Add new interface to support macro mode index query 2017-03-30 14:44:33 +02:00
XiaoYuan Zheng
6164f23a91 amdgpu/addrlib: add tcCompatible htile addr from coordinate support. 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
8b110f0319 amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex and AddrConvertTileInfoToHW
When clients queries tile Info from tile index and expects accurate
tileSplit info,  bits per pixel info is required to be provided since
this is necessary for computing tileSplitBytes; otherwise Addrlib will
return value of "tileBytes" instead if bpp is 0 - which is also
current logic. If clients don't need tileSplit info, it's OK to pass
bpp with value 0.
2017-03-30 14:44:33 +02:00
Xavi Zhang
2bf243f7c6 amdgpu/addrlib: add dccRamSizeAligned output flag
This flag indicates to the client if this level's DCC memory is aligned
or not. No aligned means there are padding to the end.
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
e443b48966 amdgpu/addrlib: Change comment alignment
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
e06aeaf19f amdgpu/addrlib: style changes and minor cleanups
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Xavi Zhang
f12d430c59 amdgpu/addrlib: add disableLinearOpt flag 2017-03-30 14:44:33 +02:00
Xavi Zhang
b5d8120a07 amdgpu/addrlib: Add GetMaxAlignments 2017-03-30 14:44:33 +02:00
Xavi Zhang
3614999878 amdgpu/addrlib: Rewrite tile mode optmization code
Note: remove reference to degrade4Space and use opt4Space instead.
2017-03-30 14:44:33 +02:00
Carlos Xiong
c12e35065a amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.
Even if surface info input flag "tcComaptible" is enabled, tc
compatible may be not supported if tile split happens for depth
surfaces. Add a new flag in output structure to notify client to
disable tc compatible in this case.
2017-03-30 14:44:33 +02:00
Xavi Zhang
2ffb30c2af amdgpu/addrlib: Make comments shorter
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
XiaoYuan Zheng
3c7bd4e013 amdgpu/addrlib: add new flag nonSplit
Flag tcCompatible has different usage in CI and VI. Add a new flag
"nonSplit" for CI.
2017-03-30 14:44:33 +02:00
Dave Airlie
69fca64259 amd/addrlib: move addrlib from amdgpu winsys to common code
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-06 10:06:33 +10:00
Renamed from src/gallium/winsys/amdgpu/drm/addrlib/addrinterface.h (Browse further)