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amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calculated correctly

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This commit is contained in:
Nicolai Hähnle 2016-07-20 10:51:50 +02:00 • committed by Marek Olšák
parent 33c25655c1
commit 48bf5d0800
2 changed files with 18 additions and 0 deletions
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2
src/amd/addrlib/addrinterface.h
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@ -906,6 +906,8 @@ typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT
UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape
UINT_32 macroHeight; ///< Macro height in pixels
UINT_64 sliceSize; ///< Slice size, in bytes.
BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved
/// Compute engine clear can't be used if htile is interleaved
} ADDR_COMPUTE_HTILE_INFO_OUTPUT;
/**

16
src/amd/addrlib/core/addrlib1.cpp
View file

@ -1295,6 +1295,22 @@ ADDR_E_RETURNCODE Lib::ComputeHtileInfo(
&pOut->macroHeight,
&pOut->sliceSize,
&pOut->baseAlign);
if (pIn->flags.tcCompatible && (pIn->numSlices > 1))
{
pOut->sliceSize = pIn->pitch * pIn->height * 4 / (8 * 8);
const UINT_32 align = HwlGetPipes(pIn->pTileInfo) * pIn->pTileInfo->banks * m_pipeInterleaveBytes;
if ((pOut->sliceSize % align) == 0)
{
pOut->sliceInterleaved = FALSE;
}
else
{
pOut->sliceInterleaved = TRUE;
}
}
}
}